View GC4116_1244387.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

GRAYCHIP
DSP CHIPS AND SYSTEMS 2185 Park Blvd.,
(650) 323-2955 FAX (650) 323-0206 Palo Alto, CA 94306
GC4116 MULTI-STANDARD QUAD DUC CHIP DATA SHEET
REV 1.0
APRIL 27, 2001
This datasheet may be changed without notice. Graychip reserves the right to make changes in circuit design and/or specifications at any time without notice. The user is cautioned to verify that datasheets are current before placing orders. Information provided by Graychip is believed to be accurate and reliable. No responsibility is assumed by Graychip for its use, nor for any infringement of patents or other rights of third parties which may arise from its use. No license is granted by implication or otherwise under any patent rights of Graychip.
(c) Graychip, Inc. All rights reserved 1999-2001
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
REVISION HISTORY
Revision
0.1 0.2 0.3 1.0
Date
Feruary 8, 2000 March 22, 2000 October 31, 2000 April 27, 2001 Original
Description
Corrected typos, and miscellaneous errors. Rewritten throughout to reflect new modes, final design changes Modified to reflect Production specifications. Changes throughout.
(c) 1999-2001 GRAYCHIP,INC.
-i-
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
CONTACTING GRAYCHIP CORPORATE OFFICES: GRAYCHIP, Inc. 2185 Park Blvd. Palo Alto, CA 94306 PHONE: (650) 323-2955 FAX: (650) 323-0206 WEB PAGE: www.graychip.com E-MAIL: sales@graychip.com tech-support@graychip.com
DATA SHEET REV 1.0
(c) 1999-2001 GRAYCHIP,INC.
- ii -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
1.0 2.0 3.0
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16
DATA SHEET REV 1.0
KEY FEATURES ........................................................................................................................ 1 BLOCK DIAGRAM ..................................................................................................................... 1 FUNCTIONAL DESCRIPTION ................................................................................................... 2
CONTROL INTERFACE ....................................................................................................................... 2 CHANNEL INPUT FORMAT ................................................................................................................. 4 THE UP-CONVERTERS ...................................................................................................................... 5 THE OVERALL INTERPOLATION FILTER RESPONSE ..................................................................... 9 THE SUM TREE .................................................................................................................................. 10 OVERALL GAIN .................................................................................................................................. 10 FOUR CHANNEL RESAMPLER ........................................................................................................ 11 SERIAL CONTROLLER ...................................................................................................................... 14 CLOCKING ......................................................................................................................................... 15 POWER DOWN MODES.................................................................................................................... 15 SYNCHRONIZATION ......................................................................................................................... 15 INITIALIZATION ................................................................................................................................. 16 DATA LATENCY................................................................................................................................. 17 DIAGNOSTICS .................................................................................................................................... 17 JTAG ................................................................................................................................................... 17 MASK REVISION REGISTER ............................................................................................................. 18
4.0 5.0
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11
PACKAGING ............................................................................................................................ 19 CONTROL REGISTERS .......................................................................................................... 23
GLOBAL REGISTERS......................................................................................................................... 23 PAGED REGISTERS ......................................................................................................................... 29 FREQUENCY AND PHASE PAGES (PAGES 0 AND 1)..................................................................... 30 INPUT GAIN PAGE (PAGE 2)............................................................................................................. 31 CHANNEL INPUT PAGE (PAGE 3) .................................................................................................... 32 RESAMPLER INPUT PAGE (PAGE 4) ............................................................................................... 33 I/O CONTROL PAGE (PAGE 7) .......................................................................................................... 34 RESAMPLER CONTROL PAGE (PAGE 8)......................................................................................... 38 RESAMPLER RATIO PAGE (PAGE 9) ............................................................................................... 40 PFIR COEFFICIENT PAGES (PAGES 16 to 31) ................................................................................ 41 RESAMPLER COEFFICIENT PAGES (PAGES 32-63) ...................................................................... 42
6.0
6.1 6.2 6.3 6.4 6.5
SPECIFICATIONS..................................................................................................................... 43
ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 43 RECOMMENDED OPERATING CONDITIONS .................................................................................. 43 THERMAL CHARACTERISTICS......................................................................................................... 43 DC CHARACTERISTICS..................................................................................................................... 44 AC CHARACTERISTICS..................................................................................................................... 45
7.0
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15
APPLICATION NOTES ............................................................................................................. 46
POWER AND GROUND CONNECTIONS .......................................................................................... 46 STATIC SENSITIVE DEVICE.............................................................................................................. 46 MOISTURE SENSITIVE PACKAGE.................................................................................................... 46 THERMAL MANAGEMENT................................................................................................................. 46 REFERENCE DESIGNS ..................................................................................................................... 47 EXAMPLE PFIR FILTER SETS........................................................................................................... 49 EXAMPLE RESAMPLER CONFIGURATIONS ................................................................................... 49 NOISE ANALYSIS ............................................................................................................................... 49 EXAMPLE GSM APPLICATION.......................................................................................................... 49 EXAMPLE IS-136 DAMPS APPLICATION.......................................................................................... 49 EXAMPLE IS-95 NB-CDMA APPLICATION........................................................................................ 49 EXAMPLE UMTS WB-CDMA APPLICATION ..................................................................................... 49 DIAGNOSTICS .................................................................................................................................... 49 OUTPUT TEST CONFIGURATION..................................................................................................... 49 INPUT TEST CONFIGURATION......................................................................................................... 49
(c) 1999-2001 GRAYCHIP,INC.
- iii -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP LIST OF FIGURES
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17:
DATA SHEET REV 1.0
GC4116 Block Diagram ........................................................................................................................................................ 1 Normal Control I/O Timing .................................................................................................................................................... 3 Edge Write Control Timing .................................................................................................................................................... 3 Serial Input Formats .............................................................................................................................................................. 4 The Up-converter Channel ................................................................................................................................................... 5 Typical PFIR Specifications .................................................................................................................................................. 6 Five Stage CIC Interpolate by N Filter .................................................................................................................................. 7 NCO Circuit ........................................................................................................................................................................... 8 Example NCO Spurs ............................................................................................................................................................. 8 NCO Peak Spur Plot ............................................................................................................................................................. 8 Overall Filter Response ........................................................................................................................................................ 9 Resampler Channel Block Diagram .................................................................................................................................... 11 The Resampler's Spectral Response ................................................................................................................................. 12 Resampler Serial Output ..................................................................................................................................................... 14 160 Pin Plastic Ball Grid Array (PBGA) Package ............................................................................................................... 19 Reference Design Without the Resampler .......................................................................................................................... 47 Reference Design Using the Resampler ............................................................................................................................. 48
LIST OF TABLES
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Sync Modes ........................................................................................................................................................................ 16 Sync Descriptions ............................................................................................................................................................... 16 Mask Revisions ................................................................................................................................................................... 18 GC4116 Pin Out Locations Top View ................................................................................................................................. 20 GLOBAL CONTROL REGISTERS ..................................................................................................................................... 23 Page Assignments .............................................................................................................................................................. 29 IO Control Page Registers (Page 5) .................................................................................................................................... 34 Resampler Control Registers .............................................................................................................................................. 38 Resampler Ratio Page ........................................................................................................................................................ 40 PFIR Coefficient Pages........................................................................................................................................................ 41 Resampler Coefficient Pages (Single filter mode) .............................................................................................................. 42 Absolute Maximum Ratings ................................................................................................................................................ 43 Recommended Operating Conditions ................................................................................................................................. 43 Thermal Data ...................................................................................................................................................................... 43 DC Operating Conditions .................................................................................................................................................... 44 AC Characteristics ............................................................................................................................................................... 45
(c) 1999-2001 GRAYCHIP,INC.
- iv -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
1.0
* * * * * * * * * * * * * * * *
KEY FEATURES
Output rates up to 100 MSPS Four identical up-convert channels 16 bit real or complex inputs Four bit serial input ports, or memory mapped input registers Serial interface controller simplifies interfacing with ASICs or DSP chips Resampler circuit filters, pulse shapes and resamples data to allow arbitrary input to output sample rate conversion Interpolation factors of 32 to 5,792 in each channel 16 to 32 by combining two channels Independent frequency, phase and gain controls User programmable 63 tap input filter 0.02 Hz tuning resolution 115 dB Spur Free Dynamic Range 90 dB or more image rejection 0.07 dB gain resolution 0.05 dB peak to peak passband ripple The four channels are summed into a single output signal 22 bit sum I/O path to merge outputs from multiple GC4116 chips * * * * * * * * 8 to 22 bit 2's complement or offset binary output samples Accepts QPSK or QAM symbol data directly, performs transmit (pulse shape) filtering Performs pulse shaping and phase equalization for IS95 and CDMA2000 Exceeds Damps, GSM, & IS95 requirements Supports up to two 4 Mbaud channels. Microprocessor interface for control Built in diagnostics Each GC4116 chip upconverts: Four GSM, DAMPS, or 1X CDMA carriers, or Two 3X CDMA2000 carriers, or Two 3.84MB UMTS carriers Power consumption at 70 MHz, 2.5 volts: 84 mW per DAMPS channel 107 mW per GSM channel 305mW per 3.84MB UMTS channel Industrial temperature range (-40C to +85C) GC4016-PB 160 ball PBGA (15mm by 15mm) package 3.3volt I/O voltage, 2.5volt core voltage JTAG Boundary Scan
*
* * * *
2.0
SUM IN
22 BITS
BLOCK DIAGRAM
SCALE & ROUND
22 BITS
SUM OUT
(8 to 22 BITS)
CHANNEL A SINA, SFSA, SCKA
16 BITS
16 BITS
16 BITS
16 BITS
SINC, SFSC, SCKC SIND, SFSD, SCKD (CHANNEL INPUTS)
SERIAL INPUTS
FILTER (CIC)
CHANNEL B 63 TAP PROGRAMMABLE INTERPOLA TE BY 2 FILTER (PFIR) 31 TAP INTERPOLA TE BY 2 FILTER (CFIR)
TUNING FREQUENCY PHASE OFFSET INTERPOLA TE
16 BITS
SINE/ COSINE GENERATOR
16 BITS
16 BITS
16 BITS
JTAG BOUNDARY SCAN LOGIC AND GAIN INPUT
TMS TDI TDO
FILTER (CIC)
20 BITS
TCK
BY 8 TO 2K
20 BITS
SINB, SFSB, SCKB
63 TAP PROGRAMMABLE INTERPOLA TE BY 2 FILTER (PFIR)
31 TAP INTERPOLA TE BY 2 FILTER (CFIR)
INTERPOLA TE BY 8 TO 2K
SIA SIB
16 BITS
16 BITS
16 BITS
16 BITS
20 BITS
SYNC COUNTER AND DIAGNOSTIC TEST GENERATOR
CHANNEL C SO 63 TAP PROGRAMMABLE INTERPOLA TE BY 2 FILTER (PFIR) 31 TAP INTERPOLA TE BY 2 FILTER (CFIR)
TUNING FREQUENCY PHASE OFFSET INTERPOLA TE BY 8 TO 2K FILTER (CIC)
SINE/ COSINE GENERATOR
23 BITS
DIVIDE BY 16
19 BITS
SCFSA SCFSB SCSTART SERIAL CONTROLLER SCFSC SCFSD
CK, CK2X
CLOCK DOUBLING AND DISTRIBUTION CIRCUIT CHANNEL D 63 TAP PROGRAMMABLE INTERPOLA TE BY 2 FILTER (PFIR) 31 TAP INTERPOLA TE BY 2 FILTER (CFIR)
TUNING FREQUENCY PHASE OFFSET INTERPOLA TE
16 BITS
SINE/ COSINE GENERATOR RINA, RFSA, RCKA RINB, RFSB, RCKB
16 BITS 20 BITS
SCCK0, SCCK1
ROUTA FOUR CHANNEL RESAMPLER ROUTB ROUTC ROUTD ROFS0, ROFS1
16 BITS
16 BITS
BY 8 TO 2K FILTER (CIC)
RINC, RFSC, RCKC RIND, RFSD, RCKD
WRMODE
CONTROL INTERFACE
PARALLEL INPUTS CHREQ TUNING FREQUENCY PHASE OFFSET SINE/ COSINE GENERATOR RSTART
ROCK0, ROCK1 RREQ
CE WR RD A[0:4] C[0:7]
Figure 1. GC4116 Block Diagram
(c) 1999-2001 GRAYCHIP,INC. -1APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
3.0
FUNCTIONAL DESCRIPTION
3.1
CONTROL INTERFACE
The GC4116 quad transmit chip contains four identical up-conversion channels. The up-convert channels accept real or complex signals, interpolate them by programmable amounts ranging from 32 to 5,792, and modulates them up to selected center frequencies. The modulated signals are then summed together and optionally summed with modulated signals from other GC4116 chips. Channels can be used in pairs to reduce the interpolation ratio down to 16 in order to process wider band input signals. Each channel contains a user programmable input filter (PFIR) which can be used to shape the transmitted signal's spectrum, or can be used as a Nyquist transmit filter for shaping digital data such as QPSK, GMSK or QAM symbols (See Section 7 for example applications). The up-converter channels are designed to maintain over 115 dB of spur free dynamic range. Each up-convert channel accepts 16 bit inputs (bit serial) and produces 20 bit outputs. The up-converter outputs are summed with an external 22 bit input to produce a single 22 bit output. The chip can output either real or complex data. The frequencies and phase offsets of the four sine/cosine sequence generators can be independently specified, as can the gain of each circuit. Each channel interpolates by the same amount, but can be programmed with independent PFIR coefficients. Channels can be synchronized to support beamformed or frequency hopped systems. An independent resampler block performs resampling on up to 4 signals. The resampler has its own input and output pins so that it can be used independently from the up-convert channels. The resampler engine is identical to the one in the gc4016. It provides a user programmable filter up to 512 taps long and allows for sampling by arbitrary amounts with delay resolutions up to 64 time phases. A serial controller block is used to generate serial clocks and frame strobes for the channel and resampler input ports. This block simplifies interfacing the GC4116 to other devices. On chip diagnostic circuits are provided to simplify system debug and maintenance. The chip receives configuration and control information over a microprocessor compatible bus consisting of an 8 bit data I/O port, a 5 bit address port, a chip enable strobe, a read strobe and a write strobe. The chip's 110 control registers (8 bits each) and five coefficient RAM's are memory mapped into the 5 bit address space of the control port using an internal page register.
The chip is configured by writing control information into control registers within the chip. The control registers are grouped into 8 global registers and 64 pages of registers, each page containing up to 16 registers. The global registers are accessed as addresses 0 through 15. Address 15 is the page register which selects which page is accessed by addresses 16 through 31. The contents of these control registers and how to use them are described in Section 5. The registers are written to or read from using the C[0:7], A[0:4], CE, RD and WR pins. Each control register has been assigned a unique address within the chip. This interface is designed to allow the GC4116 chip to appear to an external processor as a memory mapped peripheral (the pin RD is equivalent to a memory chip's OE pin). An external processor (a microprocessor, computer, or DSP chip) can write into a register by setting A[0:4] to the desired register address, selecting the chip using the CE pin, setting C[0:7] to the desired value and then pulsing WR low. The data will be written into the selected register when both WR and CE are low and will be held when either signal goes high. An alternate "edge write" mode can be used to strobe the data into the selected register when either WR or CE goes high. This is useful for processors that do not guarantee valid data when the write strobe goes active, but guarantee that the data will be stable for the required set up time before the write strobe goes inactive. The edge write is necessary for these processors, as some control registers (such as most sync registers) are sensitive to transient values on the C[0:7] data bus. To read from a control register the processor must set A[0:4] to the desired address, select the chip with the CE pin, and then set RD low. The chip will then drive C[0:7] with the contents of the selected register. After the processor has read the value from C[0:7] it should set RD and CE high. The C[0:7] pins are turned off (high impedance) whenever CE or RD are high or when WR is low. The chip will only drive these pins when both CE and RD are low and WR is high. One can also ground the RD pin and use the WR pin as a read/write direction control and use the CE pin as a control I/O strobe. Figure 2 shows timing diagrams illustrating both I/O modes.
(c) 1999-2001 GRAYCHIP,INC.
-2-
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
CE WR RD A[0-4] C[0-7] CE WR RD A[0-4] C[0-7]
tREC tCSU tCSU tCDLY
READ CYCLE- NORMAL MODE
tREC
tCZ
tREC tCSU tCSU
tCSPW
tREC
tCHD
WRITE CYCLE- NORMAL MODE
CE WR A[0-4] C[0-7] CE WR A[0-4] C[0-7]
tREC tCSU tCDLY
READ CYCLE- RD HELD LOW
tREC tCZ
tREC tCSU
tCSPW tREC tCHD
WRITE CYCLE- RD HELD LOW
Figure 2. Normal Control I/O Timing
The edge write mode, enabled by the WRMODE input pin, allows for rising edge write cycles. In this mode the data on the C[0:7] pins only need to be stable for a small setup time before the rising edge of the write strobe, and held for a small hold time afterwards. This mode is appropriate for processors that do not provide stable data before the start of the write pulse. Figure 3 shows the timing for this mode. The setup, hold and pulse width requirements for control read or write operations are given in Section 6.0.
CE WR RD A[0-4]
tREC tCSU tCSU
tCSPW
tREC
tCHD C[0-7]
EDGE WRITE MODE
tCSU
Figure 3. Edge Write Control Timing
(c) 1999-2001 GRAYCHIP,INC.
-3-
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
The bit serial samples are always entered MSB first. Complex values are entered I-half first followed by the Q-half. Real values are entered as pairs of samples, with the first sample in the I-half and the second sample in the Q-half. The input accepts either pairs of 16 bit words each with its own frame strobe (the unpacked mode), or as a single 32 bit transfer with a single frame strobe (the packed mode). The bit serial input formats are shown in Figure 4 Figure 4a shows the unpacked input mode (PACKED in the input control register is low). The user provides a bit serial clock (SCK), a frame strobe (SFS) and a data bit line (SIN). The chip clocks SFS and SIN into the chip on the rising edge of SCK (or falling edge if the SCK_POL bit in the input control register is set). The user sends a 16 bit serial input word to the GC4116 by setting SFS high (or low if SFS_POL in the input control register is set) for one SCK clock cycle, and then transmitting the data, MSB first, on the next 16 SCK clocks. The SFS may remain high during the transfer, but must go low for one SCK cycle before the next serial word is sent. The serial sample is transferred to a parallel register on the next SCK clock. Additional SCK clocks are acceptable but are ignored. The data can be transmitted "back to back" as shown in Figure 4b as long as the SFS signal toggles low and then high as shown. If the PACKED control bit is high, then the I and Q samples (or I0 then I1 for real data) are sent as a single 32 bit word with only one SFS strobe as shown in Figure 4c.:
3.2
CHANNEL INPUT FORMAT
The input samples are 16 bits, either real or complex. The samples are input to the chip either through the bit-serial input ports, or through memory mapped control registers. The channel data request signal (CHREQ) is output from the chip to identify when the GC4116 is ready for another complex input sample or pair of real samples.
3.2.1 Bit Serial Interface
The bit serial format consists of a data input pin (SIN), a bit clock pin (SCK), and a frame strobe pin (SFS) for each of the four channels (A,B,C and D), and a channel data request pin (CHREQ) which is common to all channels. The serial channel inputs can come directly from the Four Channel Resampler by connecting the resampler's serial output ports to the channel's serial input ports, and connecting the CHREQ pin to the resampler's RSTART pin. The Resampler and its I/O interface is described in Section 3.7. If the Resampler is not being used, then the Serial Controller can be used to generate the proper serial clocks and frame strobes fro the channel inputs. In this case CHREQ is tied to SCSTART, and then SCCK and the SCFS strobes are used to drive the serial clock and frame strobes for both the channel inputs and the channel data source (typically a DSP chip, FPGA, or ASIC).
SCK
TSU THD (must go low before next transfer) TSU
I15
SFS SIN
THD
I14 I13 I3 I2
I1
I0
(a) UNPACKED MODE
SCK SFS SIN
I15 I14 I13 I3 I2 I1 I0 Q15
(b) 16 BIT MODE, BACK TO BACK TRANSFER
SCK
(SFS occurs once at beginning of the 32 bit transfer)
SFS SIN
I15 I14 I13 I3 I2 I1 I0 Q15
(c) 32 BIT "PACKED" MODE
Figure 4. Serial Input Formats
(c) 1999-2001 GRAYCHIP,INC. -4APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
The GC4116 input interface sends a channel data request strobe (CHREQ) when a new input sample is required for the up-converter channels. The CHREQ strobe is output from the chip every 4N clocks, where N is the interpolation ratio in the CIC filter. The pulse width of the CHREQ strobe is one CK period. The polarity of CHREQ is user programmable. The CHREQ strobe is typically connected to SCSTART of the serial request controller, or to RSTART of the resampler (See Section 3.7.9). CHREQ can also be used as an interrupt to an external device to tell it to send another input sample. The GC4116 chip must receive the last data bit at least one bit clock (SCK) period before the next CHREQ strobe. The frame sync can be sent up to 7 bit clocks before CHREQ. This is normally used when the serial interface timing is tight, i.e., the CHREQ rate is less than 34 SCK cycles, so that there is not time between CHREQ strobes to send SFS, then 32 bits and then have an SCK cycle before the next CHREQ. Very Important Note: The chip requires that SCK be active when frame sync occurs, and be active for one cycle after the last bit is sent. Serial data can be sent using only 32 SCK clocks per CHREQ period if the frame sync for the 16 bit I word (or the 32 bit I/Q word in the PACKED mode) is coincident with the last bit of the previous transfer. The Serial Controller block described in Section 3.8 can provide appropriately timed frame strobes and serial clocks.
DATA SHEET REV 1.0
be done before the next CHREQ strobe is received. See global address 14 for handshake details.
3.3
THE UP-CONVERTERS
Each up-converter channel uses a two stage interpolate by four filter and a 5 stage cascaded integrate-comb (CIC) filter to increase the sample rate of the input data up to the chip's clock rate. An NCO and mixer circuit modulates the signal up to the desired center frequency. A block diagram of each up-convert channel is shown in Figure 5. Each input sample is multiplied by an 8 bit 2's complement gain word. The gain adjustment is GAIN/128, where the gain word (GAIN) ranges from -128 to +127. This gives a 42 dB gain adjustment range. Setting G to zero clears the channel input. A different gain can be specified for each channel. The gain values are double buffered and may be transferred to the active register on a sync. The transfer is delayed so that the new values take effect on the same sample for all channels. Gain is described in more detail in Section 3.6. After the gain has been applied, the input samples are interpolated by a factor of 2 in a 63 tap filter with programmable coefficients (PFIR). A typical use of the PFIR is to implement matched (root-raised-cosine) transmit filters. The PFIR will also, if desired, convert real input data to single-sideband complex data. In this mode the PFIR does not interpolate by a factor of 2. Instead it down-converts the input data by FS/4, where FS is the input sample rate, and low pass filters the result. The second interpolate by 2 filter is a 31 tap compensating filter (CFIR) which both interpolates by 2 and pre-compensates for the droop associated with the CIC filter that follows it. The CIC filter interpolates by another factor of N=(8 to 1,448) to give an overall interpolation factor of 32 to 5,792 (16 to 2,896 in the real input mode).
SCALE and BIG_SHIFT SHIFT DOWN
3.2.2 Memory Mapped Interfaced
Input samples can be entered into the chip using the control interface. Addresses 16 through 31 on page 3 are the input data registers. Note that these registers can be written to in a DMA burst, 8 bits at a time. Note that some DMA formats write samples most significant byte first. If this is the case then the DMA should write from address 31 down to address 16. The CHREQ strobe from the GC4116 chip defines when the DMA transfer can start. The transfer must
PFIR TAPS
GAIN
PFIR FILTER INTERPOLATE BY 2
CFIR FILTER INTERPOLATE BY 2
INPUT GAIN
I FROM INPUT FORMATTER Q
CIC FILTER INTERPOLATE BY 8 TO 2K
N
cosine
OUT
sine TUNING FREQUENCY PHASE OFFSET
NCO
Figure 5. The Up-converter Channel
(c) 1999-2001 GRAYCHIP,INC. -5APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
The interpolated signal is modulated by a sine/cosine sequence generated by the NCO. In the real output mode the real part (I-half) of the complex result is saved as the channel output. In the complex output mode the CIC interpolation is cut in half and the NCO/mixer calculates both the I-half and Q-half of the complex result. In this mode the complex output sample rate is one-half the clock rate, with the I and Q halves multiplexed together onto the same output bus.
0 dB
DATA SHEET REV 1.0
Signal of Interest Passband (Typically 0.25 to 0.4 of FIN) Narrow transition band Power Image Reject Stopband (Typically starts between 0.6 and 0.75 FIN) 0 FIN/2 FIN Frequency
-100 dB
Figure 6. Typical PFIR Specifications
the filter if the sum of the 63 coefficients is equal to 65536. If the sum is not 65536, then PFIR will introduce a gain equal to:
PFIR_SUM PFIR_GAIN = --------------------------65536
3.3.1 The Programmable Interpolate By 2 Filter (PFIR)
The input samples are filtered by two stages of interpolate by 2 filtering before they are interpolated by the CIC filter. The first stage interpolate by two filter is a 63 tap filter with programmable 16 bit coefficients. The PFIR will accept either complex or real input data. If the input samples are complex, the filter doubles the input rate by inserting zeroes between each sample, and then low pass filters the result. If the input samples are real (REAL in address 1 is set), the filter translates the real samples down by FIN/4, where FIN is the input sample rate, by multiplying them by the complex sequence +1, -j, -1, +j, ..., and then lowpass filters the result. This generates a single-sideband modulation of the real input. Note that in the real input mode the data is entered as pairs of samples packed into the complex input word format (see Section 3.2). If double sideband real upconversion is desired, then the chip should be operated in the complex mode with the Q-half of each complex pair set to zero. The PFIR filter passband must be flat in the region of the signal of interest, and have the desired out of band rejection in the region that will contain the interpolation image. Figure 6 illustrates the passband and stopband requirements of the filter. FIN is the input sample rate to the channel. 2FIN is the output sample rate of the PFIR. A common use of the PFIR is to pulse shape digital data. The PFIR will accept QPSK, O-QPSK, PSK, PAM, OOK,
, where PFIR_SUM is the sum of
the 63 coefficients. The 63 coefficients are identified as coefficients h0 through h62, where h31 is the center tap. The coefficients are assumed to be symmetric, so only the first 32 coefficients (h0 through h31) are loaded into the chip. A non-symmetric mode (NO_SYM_PFIR in address 26) allows the user to download a 32 tap non-symmetric filter as taps h0 through h31. The newest sample is multiplied by h31 and the oldest is multiplied by h01.
3.3.2 The Compensating Interpolate by 2 Filter (CFIR)
The second stage filter is a fixed coefficient 31 tap interpolate by 2 filter. The second stage filter always interpolates by a factor of two. The second filter has a passband which is flat (0.01 dB ripple) out to 0.6FIN and provides over 90dB of image rejection beyond 1.4FIN. The second filter also compensates for the droop associated with the CIC interpolation filter described in the next section. The 16 unique coefficients of the symmetric filter are: -34, -171, -166, 403, 837, -317, -1983, -790, 2820, 3328, -1667, -6589, -4024, 7232, 20602, 26577 The passband of this filter is wide enough to upconvert digital symbol data with excess bandwidths up to 0.35. The CFIR output is scaled to have unity gain. The output rate of the CFIR filter is 4FIN in the complex input mode and is 2FIN in the real input mode. The CFIR output rate relative to the clock rate is FCK/N
/4-QPSK,
or QAM symbols
and then filter them by the desired pulse shaping filter, which is commonlt a root-raised-cosine (RRC) filter. The symbols can be entered directly into the chip at the desired symbol (baud) rate. The application notes in Section 7 describes sample filter coefficients sets for common standards (DAMPS, GSM, IS95, UMTS). Each channel has its own PFIR coefficient memory, so the same filter, or a different filter, can be used in each channel. The user downloaded filter coefficients are 16 bit 2's complement numbers. Unity gain will be achieved through
(c) 1999-2001 GRAYCHIP,INC.
-6-
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
16 BITS
ZERO PAD BY FACTOR OF N
SCALE AND ROUND CLOCKED AT FULL RATE
DATA IN CLOCKED AT 1/N RATE
16 BITS
DATA OUT
Figure 7. Five Stage CIC Interpolate by N Filter 3.3.3 The CIC Interpolate by N Filter
The CFIR output is interpolated by a factor of N in the CIC1 filter, where N is any integer between 8 and 1,448. The filter is a 5 stage CIC filter. A block diagram of the CIC filter is shown in Figure 7.The output of the CIC interpolation filter is equal to the clock rate. The CIC filter has a gain equal to N4 which must be removed by the "SCALE AND ROUND" circuit shown in Figure 7. This circuit has a gain equal to 2-(3+SCALE+12*BIG_SHIFT), where SCALE ranges from 0 to 15 and BIG_SHIFT ranges from 0 to 2. The value chosen for BIG_SHIFT must also satisfy: 2(12*BIG_SHIFT+18) N4. Overflows due to improper gain settings will go undetected if this relationship is violated. This restriction means that N must be less than 23 for BIG_SHIFT = 0, N must be less than 182 for BIG_SHIFT = 1, and N must be less than 1449 for BIG_SHIFT = 2. Larger interpolation amounts can be achieved by using the resampler to perform interpolation. Larger interpolation amounts using the CIC can be accomplished only by reducing the signal amplitude feeding the CIC. The CIC filter must be initialized when the chip is first configured or whenever the interpolation value N or the shift value BIG_SHIFT are changed. The CIC filter is initialized using the flush controls described in Section 5.8. If the CIC is disturbed during processing due to noise, radiation particles, or due to changing N or BIG_SHIFT, then the CIC will generate wideband white noise in the output. This property is inherent in the mathematics of a CIC filter used for interpolation. This instability can be prevented by using the (See "auto flush" capability of the chip2 DISABLE_AUTO_FLUSH in control register 13). The auto flush mode detects CIC instability and automatically re-initializes the CIC. The auto flush mode requires that the gain up to the output of the CIC filter is less than or equal to unity.
3.3.4 Wideband Input Mode
The overall interpolation factor of an up convert channel is 4N. The minimum value of N is 8, which limits the maximum input sample rate to be FCK/32. If the clock rate is 100 MHz, then the maximum single channel input bandwidth is between 2 and 3 MHz. Wider input bandwidths can be handled by combining two channels into a single wideband channel using the SplitIQ mode (SPLITIQ in register 1). In the split IQ mode the complex input data is split between two channels. One channel up converts the I-half and the other channel up converts the Q-half. This allows the channels to process data at twice the rate so the minimum CIC interpolation is N=4 (rather than the previous N=8). The input data is entered as two samples per CHREQ cycle. The I-half inputs are packed into complex words (I0 with I1, for example) and input into the first channel. The Q-half inputs are packed into complex words (Q0 with Q1, for example) and input into the second channel. The channel processing the imaginary data is programmed with a phase offset of 90 degrees from the channel processing the real channel (PHASE=0x4000). In this mode, the chip can support two channels of 3.84 Mbaud UMTS signals. NOTE: The resampler can not be used in the split IQ mode since it cannot provide data in the two samples per CHREQ format.
3.3.5 Complex Output Mode
The chip may be configured to generate complex rather than real output. In this case the output is the I word followed by the Q word at half the clock rate. The QFLG signal is used to identify the Q half of the output. Complex output applies to all channels on a chip. Likewise, if any chip in a sum path is using complex output, then all chips in the sum path must do so also. The CIC in the complex mode interpolates by N, but only outputs every other sample. This means that the effective CIC interpolation is N/2 in the complex output mode. Note, however, that the CIC gain will still be a function of N, not N/2.
1. Hogenhauer, Eugene V., An Economical Class of Digital Filters for Decimation and Interpolation, IEEE transactions on Acoustics, Speech and Signal Processing, April 1981. 2. The auto flush mode is a patented feature of the chip. Use of the auto flush mode is highly recommended. CIC instability in cellular basestation chips without the auto flush feature can cause full power white noise to be transmitted on ALL frequencies, interfering with cell users in all nearby cells.
(c) 1999-2001 GRAYCHIP,INC.
-7-
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
PHASE OFFSET
32 BITS
DITHER GENERATOR
5 BITS 18 MSBs 23 MSBs
16 BITS
FREQUENCY WORD
32 BITS
SINE/COSINE LOOKUP TABLE
20 BITS
SINE/COSINE OUT
Figure 8. NCO Circuit 3.3.6 The Numerically Controlled Oscillator (NCO)
The tuning frequency of each down converter is specified as a 32 bit word and the phase offset is specified as a 16 bit word. The NCOs can be synchronized with NCOs on other chips. This allows multiple down converter outputs to be coherently combined, each with a unique phase and amplitude. A block diagram of the NCO circuit is shown in Figure 8. The tuning frequency is set to FREQ according to the formula FREQ = 232F/FCK, where F is the desired tuning frequency and FCK is the chip's clock rate. The 16 bit phase offset setting is PHASE = 216P/2, where P is the desired phase in radians ranging between 0 and 2. Note that a
dlo.nodither.894784853.ppow
positive tuning frequency should be used to upconvert the signal. A negative tuning frequency can be used to spectrally flip the spectrum of the desired signal. FREQ and PHASE are set in addresses 16 through 31 of the frequency and phase pages. The NCO's frequency, phase and accumulator can be initialized and synchronized with other channels using the FREQ_SYNC, PHASE_SYNC, and NCO_SYNC controls in addresses 8 through 11. The FREQ_SYNC and PHASE_SYNC controls determine when new frequency and phase settings become active. Normally these are set to "always" so that they take effect immediately, but can be used to synchronize frequency hopping or beam forming systems. The NCO_SYNC control is usually set to never, but can be used to synchronize the LOs of multiple channels.
dlo.dither.894784853.ppow
0
0
FREQ=5/24 FS No dither
-50
-50
Ftune = 5/24 Fs
FREQ=5/24 FS With dither
Ftune = 5/24 Fs
Gain (dB)
-105.28 dB -105 dB
Gain (dB)
-116.4 dB -116 dB
-100
-100
-150 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-150 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (Fs)
Frequency (Fs)
a) Worst case spectrum without dither
b) Spectrum with dither (tuned to same frequency)
Figure 9. Example NCO Spurs
0
0
-107 dB
-50
-50
-121 dB
Gain (dB)
-100
Gain (dB)
-100
-150 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-150 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (kHz)
a) Plot without dither or phase initialization
b) Plot with dither and phase initialization
Frequency (kHz)
Figure 10. NCO Peak Spur Plot
(c) 1999-2001 GRAYCHIP,INC. -8APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
The NCO's spur level is reduced to below -113 dB through the use of phase dithering. The spectrums in Figure 9 show the NCO spurs for a worst case tuning frequency before and after dithering has been turned on. Notice that the spur level decreases from -105 dB to -116 dB. Dithering is turned on or off using the DITHER_SYNC controls in addresses 8 through 11. The worst case NCO spurs at -113 to -116dB, such as the one shown in Figure 9(b), are due to a few frequencies that are related to the sampling frequency by multiples of FCK/96 and FCK/124. In these cases the rounding errors in the sine/cosine lookup table repeat in a regular fashion, thereby concentrating the error power into a single frequency, rather than spreading it across the spectrum. These worst case spurs can be eliminated by selecting an initial phase that minimizes the errors or by changing the tuning frequency by a small amount (50 Hz). Setting the initial phase to 4 for multiples of FCK/96 or FCK/124 (and to 0 for other frequencies) will result in spurs below -115 for all frequencies.
DATA SHEET REV 1.0
Figure 10 shows the maximum spur levels as the tuning frequency is scanned over a portion of the frequency range with the peak hold function of the spectrum analyzer turned on. Notice that the peak spur level is -107 dB before dithering and is -121 dB after dithering has been turned on and the phase initialization described above has been used.
3.4
THE OVERALL INTERPOLATION FILTER RESPONSE
The image rejection of the up-convert channel is equal to the stop band rejection of the overall interpolation filter response. The overall response is obtained by convolving the interpolated responses of the PFIR and CFIR filters and CIC filter response. The overall response and appropriate transmit masks are shown in Figure 11 for four common standards. Figure 11a shows the overall response for IS136 (also referred to as DAMPS). Figure 11b shows the response for GSM (input at 2 samples per bit). Figures 11c & d shows the response for IS95 and 3.84 MB UMTS.
IS136 Transmit Mask GSM Transmit Mask
(a) IS136
(b) GSM
TO BE GENERATED IS95 Transmit Mask
(c) IS95
(d) 3.84 MB UMTS
Figure 11. Overall Filter Response
(c) 1999-2001 GRAYCHIP,INC. -9APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
example, a crest factor of 12 dB is adequate if the final number of bits going to a DAC is 12 bits. In most cases the input data will already have the correct crest factor for the application, in which case the ratio
RMS -------------- 32768
3.5
THE SUM TREE
As shown in Figure 1, the mixer outputs are rounded to 20 bits and put into the LSBs of a 23 bit sum tree. The sum tree adds all four up-convert channels together. The 23 bit sum tree output is shifted down by four bits and rounded to 19 bits before being added into the LSBs of the external 22 bit sum input. The final 23 bit sum is either saturated to 22 bits (the MSB is checked for overflow) and output from the chip as 22 bits, or is scaled up by 0 to 7bits, rounded into the 8, 10, 12, 14, 16, 18, 20, or 22 MSBs and then output from the chip. The sum tree gain is equal to 2SUM_SCALE-7, where SUM_SCALE is 0 to 7 (See address 19 of the IO control page). Overflows in the sum tree are saturated to plus or minus full scale. The latency from SUMI[0:21] to SUMO[0:21] is eight clock cycles.
will be equal to the
crest factor (e.g., 0.2) and the gain settings in the channel should be set to unity. In some applications the input amplitude is far from random. For example, QPSK data has constant amplitude. In such cases the largest gain that guarantees no overflow can be calculated from the PFIR coefficients and normally allows a substantially higher gain than the optimal gain for random data of similar power. Note that the resampler's gain can be used to increase or decrease the RMS input level to the channels. The sum tree adds the four channels within a single GC4116 together and then adds in sums from other chips using the sum I/O ports. The 22 bit sum I/O path guarantees that no overflow will occur for systems with 8 chips (32 channels) or less. The final chip in the chain should then shift and round the result to optimize the performance of the D/A. Since this represents the sum of many channels the gain should be set with a 14 dB crest factor. The 14 dB crest factor assumes that the channels can be treated as uncorrelated signals which will result in a random, uniform amplitude distribution. If M signals are correlated, however, the amplitude gain can be M and the 1 sum tree gain should be set to ---- . Examples of correlated M signals are pure tones or modem signals that have been synchronized so that they might peak at the same time. These signals, however, require a much smaller crest factor, such as 3 dB for pure tones and 6 dB for modem signals. In this case the crest factor of 14 dB will absorb much of the difference in gain between M and M .
3.6
OVERALL GAIN
The overall gain of the chip is a function of the input gain setting (G), the sum of the programmable filter coefficients (PFIR_SUM described in Section 3.3.1), the amount of interpolation in the CIC filters (N described in Section 3.3.3), the scale circuit settings in the CIC filter (SCALE and BIG_SHIFT described in Section 3.3.3), and the sum tree scale factor (SUM_SCALE described in Section 3.5). The overall gain, excluding any resampler gain, is:
GAIN
=
G PFIR_SUM ------- 128 --------------------------- 65536
{N 2
4
- ( SCALE + 12 x BIG_SHIFT + 3 )
}{ 2
SUM_SCALE-7
}
where G and PFIR_SUM can be different for each channel, but N, SCALE, BIG_SHIFT, and SUM_SCALE are common to all channels. The resamplers gain, which precedes the input gain, is discussed in Section 3.7.6. The optimal gain setting is one which will keep the amplitude of the data within the channel as high as possible without causing overflow. For random amplitude data the recommended gain target is to keep the root-mean-squared amplitude of the data close to one-fifth (0.2) full scale (a 14 dB crest factor). This level should be maintained throughout the channel computations. This means that the products
RMS G PFIR_SUM -------------- -------- --------------------------- 32768 128 65536
If overflow does occur, then the samples are saturated to plus or minus full scale. Overflow can be monitored using the status register (address 14). The values of N and BIG_SHIFT must also satisfy N4 (see Section 3.3.3 for details). If N and BIG_SHIFT do not satisfy this relationship, then an overflow may occur which may not be detected. 2(12*BIG_SHIFT+18) If the auto flush mode is used, then the gain in the CIC must be less than or equal to unity. This means that the values of N, SCALE and BIG_SHIFT must satisfy 2(SCALE+12*BIG_SHIFT+3) N4 (see Section 3.3.3 for details).
and
4 - ( SCALE + 12 x BIG_SHIFT + 3 ) RMS G PFIR_SUM } -------------- -------- --------------------------- { N 2 32768 128 65536
should both be less than or equal to 0.2, where "RMS" is the root-mean-squared level of the input data. Other crest factors can be used depending upon the application. For
(c) 1999-2001 GRAYCHIP,INC.
- 10 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
If attenuation is necessary, for example when multiple channel outputs are to be added together, then the attenuation should be added as close to the output of the chip as is possible - preferably only at the end of the sumtree just prior to going to the D/A.
DATA SHEET REV 1.0
The Serial Controller is used to tell the resampler input buffer when the next set of serial samples is ready. The Serial Controller can also be used to generate the serial clock and frame strobes for the resampler's input ports (see Section 3.8).
3.7
FOUR CHANNEL RESAMPLER
3.7.2 Functional Description
The resampler consists of an input buffer, an interpolation filter, and an output buffer. A functional block diagram of the resampler is shown in Figure 12. The resampler's sampling rate change is the ratio NDELAY/NDEC where NDELAY and NDEC are the interpolation and decimation factors shown in Figure 12. The decimation amount NDEC is a mixed integer/fractional number. When NDEC is an integer, then the exact sampling instance is computed and there is no phase jitter. If NDEC is fractional, then the desired sampling instance will not be one of the possible NDELAY interpolated values. Instead the nearest interpolated sample is used. This introduces a timing error (jitter) of no more than 1/(2*NDELAY) times the input sample period. The input buffer accepts 16 bit data from the serial input ports or the memory mapped input registers. The input buffer serves both as a FIFO between the input and the resampler, and as a data delay line for the interpolation filter. The 64 complex word input buffer can be configured as four segments of 16 complex words each to support 4 resampler channels, or as two segments of 32 complex words each to support 2 resampler channels, or as a single segment of 64 complex words to support a single resampler channel. The number of segments is set by NCHAN in address 16 of the resampler control page. The interpolation filter zero pads the input data by a factor of NDELAY and then filters the zero padded data using a QTAP length filter. The output of the QTAP filter is then decimated by a factor of NDEC.
The GC4116 contains a resampler which can be used to feed the up-converter channels in the chip, or can be used as a general resampling resource for a signal processing system. The resampler shares the clock to the chip, but its input, output and control circuitry are independent from the rest of the chip. The resampler in the GC4116 chip is very similar to the one in the GC4016 chip. The resampler requires the use of the Serial Controller block described in Section 8. Note that the resampler only works on complex data so the up converter's real or split IQ modes, which require two real samples per complex word, can not use the resampler. Also, the maximum output sample rate from the resampler is CK/44 when it is connected to the GC4116's upconvert channels. This means the upconvert channels must interpolate by at least a factor of 44 (N>=11) when using the resampler.
3.7.1 Resampler Input Format
The resampler inputs are complex samples, 16 bits per I or Q word. The samples are input to the resampler through bit-serial input ports, or through memory mapped registers. A resampler data request signal (RREQ) is output from the chip to identify when the resampler is ready for another complex input sample. The request (RREQ) signal may not be periodic, depending upon the resampling ratio being used. The bit serial interface to the resampler functions the same as the serial interface to the channels (see Section 2) except the resampler does not support real input mode and the maximum input complex word rate is CK/34.
Interpolation Filter
Fractional Decimation
INPUT BUFFER
NDELAY
QTAP Filter Coefs
NDEC
OUTPUT BUFFER
Resampling Filter
Figure 12. Resampler Channel Block Diagram
(c) 1999-2001 GRAYCHIP,INC. - 11 APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
The resampling ratio for each channel is determined by setting the 32 bit RATIO control in addresses 16 through 31 of the resampler ratio page. The value of RATIO is defined as:
RATIO = 2 26 NDEC 26 INPUT SAMPLE RATE - = 2 ------------------------------------------------------------------- ----------------------- OUTPUT SAMPLE RATE NDELAY
DATA SHEET REV 1.0
stop band must start before FS-B/2. The user designs this filter assuming a sample rate equal to NDELAY*FS. Section 7.6 contains example resampler filters coefficient sets. Other passband and stopband responses can be used, such as root raised cosine receive filters, as desired. The resampler filter can also be used to augment the CIC, CFIR and PFIR filters' spectral response. The number of filter coefficients, QTAP, is equal to NMULT*NDELAY, where NMULT is the number of multiplies available to compute each resampler output, and NDELAY is either 4, 8, 16, 32 or 64 as will be described later. The maximum filter length is 512. The user specifies NMULT in address 17 of the resampler control page. The filter can be symmetric, or non-symmetric, as selected by the NO_SYM_RES control in address 17 of the resampler control page. The symmetric filter is of even length which means the center tap repeats. The 12 bit filter coefficients are stored in a 256 word memory which can be divided into one, two, or four equal blocks. This allows the user to store one symmetric filter of up to 512 taps, two symmetric filters of up to 256 taps each, or four symmetric filters of up to 128 taps each. The number of filters is set by NFILTER in address 16 of the resampler control page. The filter used by each channel is selected
Up to four ratios can be stored within the chip. A ratio map register (address 23) selects which ratio is used by each channel. The three spectral plots shown in Figure 13 illustrate the steps required to resample the channel data. The first spectral plot shows the data just after zero padding. The sample rate after zero padding is NDELAY*FS, where FS is the sample rate into the resampler. The second spectrum shows the shape of the QTAP filter which must be applied to the zero padded data in order to suppress the interpolation images. The last spectrum shows the final result after decimating by NDEC.
3.7.3 The Resampler Filter
Figure 13(b) illustrates the spectral shape requirements of the QTAP filter. If the desired signal bandwidth is B, then the filter's passband must be flat out to B/2 and the filter's
NDELAY Images added by zero padding Power
...
-3FS -2FS -FS -FS/2 FS/2 FS 2FS 3FS
...
Freq
a) Spectrum after zero padding
QTAP Filter Frequency Response Images reduced by Filtering Power
...
-3FS -2FS -FS -FS/2 FS/2 FS 2FS 3FS
...
b) Spectrum after filtering
In-band aliasing caused by decimation by NDEC Power
Freq
-FO
-FO/2
FO/2
Freq FO=(NDELAY/NDEC)FS
b) Final Spectrum after decimating by NDEC
Figure 13. The Resampler's Spectral Response
(c) 1999-2001 GRAYCHIP,INC. - 12 APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
using the FILTER_SEL controls in address 18 of the resampler control page. The filter lengths are cut in half if the filters are not symmetric. The coefficients are stored in memory with h0 stored in the lowest address, where h0 is the coefficient multiplied by the newest piece of data. The center tap of a symmetric filter is h(QTAP/2)-1. The coefficients for multiple filters (NFILTER>1), are interleaved in the 256 word memory.
DATA SHEET REV 1.0
Note that the resampler's output sample rate is usually much less than the clock rate, so that NMULT is rarely limited by this restriction. The value of NMULT must also be less than the size of the delay line formed by the input buffer. The size of the delay line is either 16 for four resampler channels, 32 for two channels or 64 for a single channel as set by the NCHAN control in address 16 of the resampler control page. This limits NMULT to be less than or equal to 15, 31 or 63 dependent upon the number of resampler channels1. The typical resampler configuration will have four active channels, all using the same filter and the same resampling ratio. The typical configuration has NCHAN set to 4, NFILTER set to 1, NMULT set to 15 and NO_SYM_RES set to 0. This sets NDELAY to 32 and QTAPS to 480.
3.7.4 Restrictions on NMULT
The user does not directly set the value of NDELAY. The chip sets the value of NDELAY using NO_SYM_RES, NMULT and NFILTER according to: NDELAY
= Floor_2 [ 256 ---------------------------------------------- ] ( NMULT ) ( NFILTER )
( 2 - NO_SYM_RES )
where the function FLOOR_2[X] means the power of two value that is equal to or less than "X". Since NMULT is restricted to be greater than or equal to 6 and less than or equal to 64, then NDELAY is either 4, 8, 16, 32 or 64. The length of the filter is then: QTAP = ( NDELAY ) ( NMULT ) The value of NMULT determines both the length of the filter and the number of delays in the resampling operation. In general one would choose the largest value of NMULT which gives an adequately large value of NDELAY. The choice of NMULT, however, must meet several restrictions. NMULT must be greater than a minimum, it cannot exceed the available number of multiplier cycles, and it must be less than the input delay line segment size. These restrictions are described below. The minimum value of NMULT is determined by the minimum number of clock cycles required to update the resampler's state. This is a hardware restriction imposed by the chip's architecture. This limitation is: NMULT 6 NMULT 7 if there are two or more channels if there is only one channel (NCHAN=0)
3.7.5 Resampler Shift and Round
The gain of each resampler output is adjusted by an up-shift by 0-15 bits (FINAL_SHIFT). This up-shift is applied just before rounding to 12, 16, 20 or 24 bits (ROUND). The values of FINAL_SHIFT and ROUND are set in control register 19 of the resampler control page. The resampler gain is:
RES_SUM RES_GAIN = ( ----------------------------------------------- ) ( 2 32768 x NDELAY FINAL_SHIFT
)
where RES_SUM is the sum of the QTAP coefficients.
3.7.6 By-Passing the Resampler
The resampler is bypassed by using a configuration which has h0 set to 1024, all other taps set to zero, NMULT set to 7, NO_SYM_RES set to 1, FINAL_SHIFT set to 5, and RATIO set to 226 (0x04000000). Note that the NDELAY term in the RES_GAIN equation shown above does not apply in this case and should be set to unity in the gain equation.
3.7.7 Resampler Output Buffer
The resampler output buffer stores resampler outputs until they are needed. The output is double buffered so that samples from each channel can be stored while previous samples are being output. Resampler output samples are held in the buffer until the RSTART signal is received. When RSTART is received, the buffered data is transferred to the serial output ports which begin to output the samples as
The maximum value of NMULT must be less than, or equal to, twice the number of clock cycles available to calculate a resampler output. NMULT is the number of multiplier cycles used by the resampler to calculate each output. Since the resampler can perform two multiplies every clock cycle, the value of NMULT cannot exceed two times the number of clock cycles available to the resampler for each channel. The number of clock cycles available to the resampler is equal to the clock rate to the chip divided by the sum of the output sample rates for each resampler channel.
1. NOTE: If the resampler is being used at much less than its maximum capacity, i.e., NMULT is much less than twice the number of clock cycles available (See also RES_CLK_DIV), AND the channels are synchronous, then NMULT may equal the size of the delay line.
(c) 1999-2001 GRAYCHIP,INC.
- 13 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
serial data streams. The RSTART pulse can only be one CK pulse wide. The resampler serial output format is shown in Figure 14. The serial frame sync (ROFS) and serial data (ROUT)
RSTART ROCK ROFS ROUT
I15 I14 I13 I12 I11 I1 I0 Q15 Q14 Q13 Q12
DATA SHEET REV 1.0
3.8
SERIAL CONTROLLER
The Serial Controller block can be used to generate the necessary serial clock and frame strobes for the channel or resampler input ports. This frees the input data source (ASIC, FPGA or DSP chip) from having to generate these signals. In the case of a DSP chip, this may allow the input samples to be transferred in a background "DMA" mode that doesn't interrupt the DSP before or after each serial transfer. The Serial controller generates a serial clock and four serial frame strobes, one for each input serial port. Each frame strobe can be programmed to be delayed by a different amount from the Serial Controller start (SCSTART) pulse. The serial controller contains a serial clock generator and a frame counter. The serial clock (SCCK) is generated by dividing down CK by 1 to 16 (see SC_CK_DIV in address 20 of the IO control page). The serial clocks in multiple chips can be synchronized by using the SIA or SIB sync inputs, as selected by the SCCK_SYNC control bits in address 20 of the IO control page. Two copies of the serial clock are output on pins SCCK0 and SCCK1. Two copies are output to increase the fanout of the clock. The start signal (SCSTART) is clocked into the chip on the rising edge of CK. SCSTART is expected to be one CK clock cycle wide. Typically SCSTART is either connected to CHREQ or RREQ, depending upon whether the it is being used for the up convert channels or the resampler. The 8 bit frame counter is started by SCSTART at the value SC_FRAME_CNT. The counter is decremented at the serial clock rate until it reaches zero. The counter will continue to decrement for 18 more serial clocks if it is being used with the resampler (SC_MODE=0 in address 17 of the IO Control page), at which time it will tell the resampler that the serial frame is done and a new resampler computation can begin. The counter will count down 2 more serial clocks and stop if the serial controller is being used with the channels (SC_MODE=1). The serial frame strobes SCFSA, SCFSB, SCFSC and SCFSD are generated by comparing the upper four bits of the frame counter to SC_FS_DELAY_A, SC_FS_DELAY_B, SC_FS_DELAY_C and SC_FS_DELAY_D. A frame strobe is output when the delay values match the counter and the lower four bits of the counter are zero. This allows the frame strobes to be generated on 16 serial clock boundaries. NOTE: If the 4 LSBs of SC_FRAME_CNT are zero, and one of the SC_FS_DELAY values match the upper 4 bits of SC_FRAME_CNT, then that frame strobe will be active when the serial controller is idle and waiting for another SCSTART
Figure 14. Resampler Serial Output
change on the rising edge of the serial clock (ROCK). The resampler serial outputs can be connected directly to the upconverter channel serial inputs if the polarity of the resampler serial clock is inverted by setting RES_CK_POL in address 18 of the resampler control page.
3.7.8 Resampler I/O Control
The Resampler will stop if the output buffer is full, or if the input buffer needs more samples. Typically the output rate is constant, such as when the resampler is feeding upconverter channels. The input rate is typically erratic, depending upon when the resampler needs more input data. The resampler start control (RSTART) is used to start the serial outputs. The RSTART control transfers data from the output buffer into the serial output registers. The serial output frame will then start on the next rising edge of ROCK1. If the output buffer is full, then the resampler will stop until the next RSTART pulse has been received. The resampler input data timing is controlled by the RREQ strobe and the Serial Controller described in the next Section. The RREQ strobe is output when the resampler needs more input data. The RREQ strobe should be connected to the SCSTART input of the Serial Controller. The Serial Controller is then programmed to tell the resampler that the serial transfer is done and new input data is ready. The frame length programmed into the Serial Controller tells the resampler that the new data samples are ready SC_FRAME_CNT+18 serial clocks after RREQ. SC_FRAME_CNT is set in address 21 of the IO control page. Note that the serial controller can be used to slow down the RREQ rate by setting the minimum period between RREQ strobes to be SC_FRAME_CNT+18 serial clocks.
1. Actually, the serial frame starts on the next rising edge of ROCK which is 2 CK pulses after RSTART.
(c) 1999-2001 GRAYCHIP,INC.
- 14 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
pulse. In general, the lower 4 bits of SC_FRAME_CNT should be non-zero. The serial control supports both the packed and unpacked serial modes, where the unpacked mode expects a serial frame strobe for each 16 bit word of a complex pair, and the packed mode expects a single frame strobe for the 32 bit complex pair. The frame strobe in the packed mode (PACKED=1 and SC_MODE=1, or RES_PACKED=1 and SC_MODE=0, in addresses 16 and 17 of the IO Control page) may be positioned in one of 15 delays, corresponding to SC_FS_DELAY values of 0 through 14. In the unpacked mode only the upper three bits of the counter are compared with the upper 3 bits of the SC_FS_DELAY values. The lower bit of the SC_FS_DELAY values must be zero. This means that the values will match twice, outputting two frame strobes, 16 bits apart. If the input data is coming from four serial streams, so that the four frame strobes should be sent at the same time, then SCFRAME_CNT should be set to 17, and the four SC_FS_DELAY values should be set to "1". Larger values of SC_FRAME_CNT can be used in this case in order to spread out the RREQ periods. If the data is coming from a single TDM bus, then SCFSA (or SCSTART) can be sent to the data source to start the TDM frame, and then SCFSB, SCFSC and SCFSD can be delayed to identify the appropriate time slots in the TDM bus. When the serial controller is being used with the channel inputs (not the resampler) and the upconvert interpolation factor is 32 or 36, then the frame delays must be used to delay the serial frames to start between 2 to 7 clocks before the next CHREQ strobe. This is because of the requirement that the serial transfer of 32 bit is completed 2 to 7 clocks before the next CHREQ strobe (See Section 3.2.1). This means that for an interpolation of 32 (the CIC interpolation factor N is 8), SC_FRAME_CNT should be set to 39 and the SC_FS_DELAY values should be "1". For an interpolation of 36 (N=9) SC_FRAME_CNT should be 43. For larger interpolation factors the default value of 17 can be used. NOTE that if the serial clock is divided, then similar delay values may need to be used in order to insure that the serial frame is complete before the next CHREQ.
DATA SHEET REV 1.0
clock rate so that the internal circuitry is clocked at twice the data rate. The clock doubler requires 4-5 clocks to adapt to the rate of the incoming clock during which time the reset should be active. A gated clock, not uniform clock period clock, is not suitable for this device above 40 MHz. A test mode (ext_2xck) allows the use of an external double rate clock (ck2x pin). This is intended for use in production test. Please contact Graychip if further information on this mode is needed.
3.10
POWER DOWN MODES
The chip has a power down and clock loss detect circuit. This circuit detects if the clock is absent long enough to cause dynamic storage nodes to lose state. If clock loss is detected, an internal reset state is entered to force the dynamic nodes to become static. The control registers are not reset and will retain their values, but any data values within the chip will be lost. When the clock returns to normal the chip will automatically return to normal. In the reset state the chip consumes only a small amount of standby power. The user can select whether this circuit is in the automatic clock-loss detect mode, is always on (power down mode), or is disabled (the clock reset never kicks in) using the DISABLE_CK_LOSS control bit in address 13 and the GLOBAL_RESET control bit in address 5. The whole chip, or individual down converter channels can be powered down. Individual channels are powered down using the RESET_A, B, C and D control bits in address 5.
3.11
SYNCHRONIZATION
Each GC4116 chip can be synchronized through the use of one of two sync input signals, an internal one shot sync generator, or a sync counter. The sync to each circuit can also be set to be always on or always off. Each circuit within the chip, such as the sine/cosine generators or the interpolation control counter can be synchronized to one of these sources. These syncs can also be output from the chip so that multiple chips can be synchronized to the syncs coming from a designated "master" GC4116 chip.
3.9
CLOCKING
The chip clock rate is equal to the output data rate which can be up to 100 MHz. An internal clock doubler doubles the
(c) 1999-2001 GRAYCHIP,INC.
- 15 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
The 2 bit sync mode control for each sync circuit is defined in Table 1:
Sync Circuit
Table 2: Sync Descriptions
Mode 1 SIA Description Interpolation control counter. Sets timing of CHREQ. Internal sync counter. Generates TC sync. Mode 2 is always ONE_SHOT The output sync (SO) selection. A single bit sync selection. GAIN_SYNC=0 means the gain is applied immediately. GAIN_SYNC=1 means the gain is applied after SIB. Selects when to start the diagnostic ramp and to store the diagnostic checksum. Selects when new frequency settings take effect. Selects when new phase settings take effect. Reset the NCO phase accumulator Clears the NCO dither circuit. Default 1(SIA)
Table 1: Sync Modes
INT_SYNC MODE 0 1 2 SYNC SOURCE off (never asserted) SIA or SIB (See Table 2) TC (terminal count of the sync counter) or ONE_SHOT (if USE_ONESHOT in address 0 is set) on (always active) COUNTER_ SYNC SIA
2 (OS)
OUTPUT_ SYNC GAIN_SYNC
SIA
2 (TC)
3
SIB
0
NOTE: the internal syncs are active high. The SIA and SIB inputs have been inverted to be the active high syncs SIA and SIB in Table1.
DIAG_SYNC SIA
2 (TC)
The ONE_SHOT sync (address 0, bit 7) can either be a level or a pulse as selected by the OS_MODE control bit in address 13. The level mode is used to initialize the chip, the pulse mode is used to synchronously switch frequency, phase or gain values. The SIA and SIB external sync inputs are provided to allow independent synchronization of different features of the GC4116 chip. Sync mode 1 is either SIA or SIB, depending upon what circuit is being synchronized by the sync circuit. Table 2 lists all of the sync circuits, what they do, which sync mode 1 it uses, and the suggested default mode settings. The SIA sync is intended to be used during initialization only. The circuits connected to SIA are ones that should be initialized once, and then let free run. SIB is intended to be used for those circuits which may be periodically initialized, such as changing frequency, phase and gain between TDMA bursts. The interpolation control counter generates the request strobe (CHREQ) output from the chip. This counter can be syncronized using the input SIA sync (INT_SYNC=1). This allows the user to lock the timing of the request strobe to the SIA timing. If this is done, and BIG_SHIFT is even, then the CHREQ strobe will go high 8 clock cycles after the SIA strobe. For example, if the SIA signal is active during clock cycle 0, then CHREQ will go high during clock cycle 8 and then repeat every 4N clocks (or 2N clocks in the real input mode) thereafter. If BIG_SHIFT is odd then the delay is 7 clock cycles.
FREQ_SYNC
SIB
3 (on)
PHASE_SYNC
SIB
3 (on)
NCO_SYNC
SIB
0 (off)
DITHER_ SYNC FLUSH _ (A,B,C,D) ROCK_SYNC
SIB
0 (off)
SIA
Starts a flush of the channel
1 (SIA)
SIA
Syncs the resampler's serial output clock. Mode 2 is SIB.
1 (SIA)
SCCK_SYNC
SIA
Syncs the serial controller's 1 (SIA) serial output clock. Mode 2 is SIB. Syncs the resampler during initialization Selects when a new resampler ratio takes effect. 2 (SIA)
RES_SYNC
Note 1
RATIO_SYNC
Note 1
3 (SIB)
Note 1: These use a 3 bit sync mode selection where modes 0,1 and 5 are "off", mode 2 is SIA, mode 3 is SIB, mode 4 is ONE_SHOT, and modes 6 and 7 are "on".
3.12
INITIALIZATION
Two initialization procedures are recommended. The first is recommended for multi-GC4116 chip configuration. The second can be used for stand alone GC4116 chips.
(c) 1999-2001 GRAYCHIP,INC.
- 16 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
3.12.1 Initializing Multiple GC4116 Chips
The multi-GC4116 initialization procedure assumes that the SIA sync input pins of all GC4116 chips are tied together and are connected to the SO output of the "master" chip, or to a common sync source. The procedure is to: (1) reset the chip by setting address 5, the reset register, to 0xFF; (2) configure the rest of the chip including setting the INT_SYNC, RES_SYNC and FLUSH_(A,B,C,D) to be SIA, the OS_MODE to be 1, and the OUTPUT_SYNC to be OS (see Table 1); (3) assert the SIA sync input by setting the ONE_SHOT control bit high (or by setting the external SIA source low); (4) release the global resets by setting address 5 to 0x00; and (5) release the SIA sync by setting ONE_SHOT to 0 (or the external SIA source high). The global resets are asserted before configuring the chip so that the operation of all of the pins, including the directions of the bidirectional and tristate pins, will be established before the global resets release them. The SIA sync is asserted before releasing the global resets so that the channels will remain in a reset state after the global resets are released. All channels and the resampler will then start synchronously by releasing the SIA sync. If there are multiple chips which need synchronized, then synchronously releasing the SIA sync to them all will force them all to be synchronized. The frequency, phase and gain of multiple chips can be initialized by holding SIB low and then releasing it to all of the chips at the same time.
3.13
DATA LATENCY
The data latency through the chip is defined as the delay from the rising edge of a step function input to the chip to the rising edge of the step function as it leaves the chip. This delay is dominated by the number of taps in each of the filters. An estimate of the overall latency through the chip, expressed as the number of CK clock cycles is: (CIC latency = 2.5N) + (CFIR latency = 16N) + (PFIR latency = N*PTAP) + (Resampler latency) + (Input delay) + (Pipeline delay) where N is the CIC interpolation ratio and PTAP is the number of PFIR taps. PTAP is normally 63. Latency can be reduced by using the NO_SYM_PFIR mode to shorten the filter. The Resampler latency, if the resampler is being used, is approximately 2N*NMULT plus a resampler input sample period and a resampler output period to allow for resampler I/O buffering. The latency in the resampler can be minimized by using the bypass configuration (See Section 3.7.7). The Input delay is approximately two input sample periods due to the double buffering in the serial input ports. The Pipeline delay is approximately 40 clock cycles.
3.14
DIAGNOSTICS
The chip has an internal ramp generator which can be used in place of the data inputs for diagnostics. An internal checksum circuit generates a checksum of the output data to verify the chip's operation. See Section 7.12 for diagnostic configurations and checksums. Besides the internal diagnostics, the chip supports initial board debug through special input and output tests. The suggested procedure for bringing up the GC4116 chip on a board is to first check the control interface by writing to the control registers and reading them back. The diagnostics described in Section 7.12 should be run next, followed by the output and input tests described in Sections 7.13 and 7.14. If these pass successfully, then the configuration customized for the desired application should work.
3.12.2 Initializing Stand Alone GC4116 chips
The initialization sequence for a stand alone GC4116 chip is similar to the one for the multi-GC4116 procedure, except that the ONE_SHOT is used to synchronize the chip, not the SIA input sync. The procedure is to: (1) reset the chip by setting address 5, the reset register, to 0xFF; (2) configure the rest of the chip including setting the INT_SYNC, RES_SYNC and FLUSH_(A,B,C,D) to be ONE_SHOT (mode 2) and the OS_MODE to be 1; (3) assert the syncs by setting ONE_SHOT high; (4) release the global resets by setting address 5 to 0x00; and (5) release the syncs by setting ONE_SHOT to 0.
3.15
JTAG
The GC4116 supports a four pin (TDI, TDO, TCK and TMS) boundary scan interface. Contact GRAYCHIP to receive the GC4116's BSDL file.
(c) 1999-2001 GRAYCHIP,INC.
- 17 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
from address 31 of page 0. The revision code allows users to determine, through software, what version of the GC4116 chips are being used. The current mask revision codes are:
3.16
MASK REVISION REGISTER
An 8 bit mask revision code (REVISION) can be read
Table 3: Mask Revisions
GC4016 Revision Code (REVISION) 0 1 2 Release Date April 2000 Nov. 2000 March 2001 Mask Code on Package SAMPLE 1002ACB 1002BCB Early samples First Release, Revision 1 Revision 2, adds JTAG, corrects initialization bug Description
(c) 1999-2001 GRAYCHIP,INC.
- 18 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
4.0
H4 H2 H1 G3 H3 G1 G2 F3 F2 E3 E1 E2 D1 D2 C1 C2 B1 B3 C3 A3 B4 C4
PACKAGING
SUMI21 SUMI20 SUMI19 SUMI18 SUMI17 SUMI16 SUMI15 SUMI14 SUMI13 SUMI12 SUMI11 SUMI10 SUMI9 SUMI8 SUMI7 SUMI6 SUMI5 SUMI4 SUMI3 SUMI2 SUMI1 SUMI0 (MSB) SUMO21 SUMO20 SUMO19 SUMO18 SUMO17 SUMO16 SUMO15 SUMO14 SUMO13 SUMO12 SUMO11 SUMO10 SUMO9 SUMO8 SUMO7 SUMO6 SUMO5 SUMO4 SUMO3 SUMO2 SUMO1 SUMO0 QFLG CHREQ A4 B5 C5 A5 B6 B7 A7 C8 C7 A8 B8 C9 A9 B9 C10 A10 B10 C11 B11 A12 B12 A13 C13 P6
0.36 mm
D1
1.53 mm 13 mm
A2
A1
0.5 mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P
A
GRAYCHIP GC4116PB QUAD DUC MMMMMM LLL YYWW
D
15 mm
M10 N10 L14 L11 M8 M9 N14 L12 H14 G13 E14 F12 M5
SCKD SCKC SCKB SCKA SFSD SFSC SFSB SFSA SIND SINC SINB SINA SCSTART
GC4116 QUAD DUC CHIP
CHANNEL I/O
TOP VIEW
MMMMMM = Mask Code LLL = Lot Number YYWW = Date Code
L
1.0 mm
SCCK1 SCCK0 SERIAL CONTROLLER I/O SCFSD SCFSC SCFSB SCFSA RREQ ROCK1 ROCK0
P11 M12 P7 N9 N12 M11 M6 P10 N11
N6 M14 M13 J13 K12 N7 P9 K13 L13 J11 G12 G11 E13 L3 L1 K2 K3 K1 M1 P2 L2 N3 J3 J1 J14 J12
RSTART RCKD RCKC RCKB RCKA RFSD RFSC RFSB RFSA RIND RINC RINB RINA A4 (MSB) A3 A2 A1 A0 RD WR CE WRMODE SIB SIA CK CK2X RESAMPLER I/O
P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14
P
1.0 mm
B
0.53 mm
ROFS1 ROFS0 ROUTD ROUTC ROUTB ROUTA (MSB) C7 C6 C5 C4 C3 C2 C1 C0
P12 M7 H13 H11 F14 E12 P5 N5 P4 M4 N4 P3 M2 M3
BOTTOM VIEW
DIMENSION D (width body) D1 (width cover) P (ball pitch) B (ball width) L (overhang) A (overall height) A1 (ball height) A2 (substrate thickness) TYP 15 mm 13 mm 1.0 mm 0.53 mm 1.0 mm 1.53 mm 0.5 mm 0.36 mm TOLERANCE mm mm mm mm mm mm mm mm
CONTROL I/O
THERMAL GND BALLS: G7, G8, H7, H8 GND BALLS: A6, D3, D12, E4, F4, F11, G14, K4, K11, N8 B2, B13, C6, D5, D9, D11, L5, L7, L8, L10, N2, N13 VCORE BALLS: VPAD BALLS: D4, D7, D14, F1, F13, G4, H12, J4, K14, P8 A2, A11, B14, D6, D8, D10, L4, L6, L9, N1, P13
SO TMS TCK TDI TDO
J2 C12 E11 D13 C14
NOTE: 0.01 to 0.1 f DECOUPLING CAPACITORS SHOULD BE PLACED AS CLOSE AS POSSIBLE TO EACH SIDE OF THE CHIP
Figure 15. 160 Pin Plastic Ball Grid Array (PBGA) Package
(c) 1999-2001 GRAYCHIP,INC.
- 19 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
Table 4: GC4116 Pin Out Locations Top View
1: A: B: C: D: E: F: G: H: J: K: L: M: N: P:
SUMI5 SUMI7 SUMI9 SUMI11 VCORE SUMI16 SUMI19 SIA A0 A3 RD VPAD
2:
VPAD GND SUMI6 SUMI8 SUMI10 SUMI13 SUMI15 SUMI20 SO A2 CE C1 GND WR
3:
SUMI2 SUMI4 SUMI3 GND SUMI12 SUMI14 SUMI18 SUMI17 SIB A1 A4 C0 WRMODE C2
4:
5:
6:
GND
7:
8:
9:
SUMO9 SUMO8
10:
SUMO6 SUMO5 SUMO7 VPAD
11:
VPAD SUMO3 SUMO4 GND TCK GND
12:
SUMO2 SUMO1 TMS GND ROUTA SINA RINC VCORE CK2X RCKA SFSA SCCK0 SCFSB ROFS1
13:
SUMO0 GND QFLG TDI RINA VCORE SINC ROUTD RCKB RFSB RFSA RCKC GND VPAD
14:
SUMO21 SUMO18 SUMI1 SUMI0 VCORE GND GND VCORE SUMI21 VCORE GND VPAD C4 C3 C5 GND SCSTART C6 C7
SUMO15 SUMO12
SUMO20 SUMO17 SUMO16 SUMO11 SUMO19 GND GND VPAD
VPAD TDO VCORE SINB ROUTB GND SIND CK VCORE SCKB RCKD SFSB
SUMO13 SUMO14 SUMO10 VCORE VPAD GND
TGND TGND
TGND TGND
RINB ROUTC RIND GND
VPAD RREQ RSTART CHREQ
GND ROFS0 RFSD SCFSD
GND SFSD GND VCORE
VPAD SFSC SCFSC RFSC
GND SCKD SCKC ROCK1
SCKA SCFSA ROCK0 SCCK1
VPAD = Pad ring power VCORE = Core power TGND = Thermal ground
(c) 1999-2001 GRAYCHIP,INC.
- 20 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
SIGNAL CK DESCRIPTION INPUT CLOCK. Active high input The clock input to the chip. The SUMI, RSTART, SCSTART, SIA and SIB input signals are clocked into the chip on the rising edge of this clock. The SUMO, CHREQ, RREQ, ROUT, ROCK, ROFS, SCCK, SCFS and SO outputs are clocked out by the rising edge of CK. DOUBLE RATE INPUT CLOCK. Active high input The chip uses an internally doubled clock for normal processing. For test purposes the double rate clock can be supplied externally using this pin. Should be grounded for normal use. SYNC IN. Active low input The sync inputs to the chip. These syncs are clocked into the chip on the rising edge of the input clock (CK). All timers, accumulators, and control counters are, or can be, synchronized to one of SIA or SIB. SYNC OUT. Active low output This signal is either a delayed version of the input sync SIA, the sync counter's terminal count (TC), or a one-shot strobe. The SO signal is clocked out of the chip on the rising edge of the input clock (CK). CHANNEL DATA REQUEST, programmable active high or low output The chip requests new input data for the channels by asserting this signal. CHREQ is clocked out of the chip on the rising edge of CK and is one CK cycle wide. The polarity of this signal is user programmable. This signal is typically connected to the RSTART input of the resampler, or the SCSTART input of the serial controller. It can also be used as a start pulse to dedicated circuitry or an interrupt to a DSP chip. BIT SERIAL INPUT DATA, Active high input The bit serial input data for the four channels. The I and Q halves of complex data are entered on the same pin. Each time the chip asserts CHREQ (See above) the I-half is entered and then the Q-half. BIT SERIAL DATA CLOCK, Active high or low input The serial data bits are clocked into the chip by these clocks. The active edge of these clocks are user programmable. BIT SERIAL FRAME STROBE, Active high or low input The bit serial word strobe. This strobe delineates the 16 bit words, or 32 bit complex pair, within the bit serial input stream. This strobe can be a pulse at the beginning of each bit serial word, or can act as a window enable which is active while the data bits are active. SIGNAL RREQ DESCRIPTION
DATA SHEET REV 1.0
CK2X
RESAMPLER REQUEST, programmable active high or low output The chip requests new input data for the resampler by asserting this signal. RREQ is clocked out of the chip on the rising edge of CK and is one CK cycle wide. The polarity of this signal is user programmable. This signal must be connected to the SCSTART input of the serial controller if the resampler is being used. It can also be used as an interrupt to a DSP chip, or as a start pulse to dedicated circuitry. RESAMPLER START, active high input This input requests the resampler to send data. Typically connected to CHREQ. RSTART is clocked into the chip on the rising edge of CK and can only be high for one CK cycle. RESAMPLER INPUT BIT SERIAL DATA, Active high input The bit serial input data for the resampler input. The I and Q halves of complex data are entered on the same pin, MSB to LSB, I-half followed by Q-half. RESAMPLER INPUT SERIAL CLOCK, Active high or low input The resampler serial data bits are clocked into the chip by these clocks. The active edge of these clocks are user programmable. RESAMPLER INPUT FRAME STROBE, Active high or low input The resampler bit serial frame strobe. This strobe delineates the 32 bit complex words within the bit serial input stream. This strobe can be a pulse at the beginning of each bit serial word, or can act as a window enable which is active while the data bits are active. RESAMPLER OUTPUT BIT SERIAL DATA, Active high output The bit serial output data from the resampler. The I and Q halves of complex data are transmitted on the same pin, I followed by Q, 16 bits each, MSB first. RESAMPLER OUTPUT SERIAL CLOCKS, programmable active high or low output These outputs provide two copies of a programmable serial clock. Normally used to drive the serial clock inputs to the channels (SCK-A,B,C,D). RESAMPLER OUTPUT FRAME STROBES, programmable active high or low output The resampler outputs a single frame strobe common to all outputs. Two copies of this signal are provided for fan out. They are normally connected to the channels (SFS-A,B,C,D).
RSTART
SIA, SIB
RIN A,B,C,D
SO
RCK A,B,C,D
CHREQ
RFS A,B,C,D
SIN A,B,C,D
ROUT A,B,C,D
SCK A,B,C,D
ROCK 0,1
SFS A,B,C,D
ROFS 0,1
(c) 1999-2001 GRAYCHIP,INC.
- 21 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
SIGNAL SCSTART DESCRIPTION SERIAL CONTROLLER START, active high input The start pulse for the serial controller. Normally connected to CHREQ or RREQ. Can only be high for one CK cycle at a time. SERIAL CONTROLLER OUTPUT CLOCKS, active high or low outputs These outputs provide two copies of a programmable serial clock. Normally used to drive both the serial clock port of a DSP, FPGA or ASIC chip and the serial clock inputs of either the resampler block (RSCK-A,B,C,D) or the channels (SCK-A,B,C,D). SERIAL CONTROLLER OUTPUT FRAME STROBES, active high or low outputs The frame strobe outputs of the serial controller. They are normally connected either to the resampler input frame strobes (RSFS-A,B,C,D) or the channel input frame strobes (SFS-A,B,C,D) as well as to a DSP, FPGA or ASIC chip's serial frame strobe input. SUM IO INPUT DATA. Active high inputs The 22 bit two's complement sum tree input samples. New samples are clocked into the chip on the rising edge of CK. The input data rate is assumed to be equal to the clock rate. SUM IO OUTPUT DATA. Active high outputs The 22 bit sum tree output data. The bits are clocked out on the rising edge of the clock (CK). Programmable two's complement or offset binary. Q FLAG. Active high output This output is high to identify the imaginary half of a complex sample. This is useful in complex output mode where I and Q are multiplexed onto the sum IO pins. QFLG is clocked out on the rising edge of CK. WRMODE SIGNAL C[0:7] DESCRIPTION
DATA SHEET REV 1.0
SCCK 0,1
CONTROL DATA I/O BUS. Active high bidirectional This is the 8 bit control data I/O bus. Control register data is loaded into the chip or read from the chip through these pins. The chip will only drive these pins when CE is low and RD is low and WR is high. CONTROL ADDRESS BUS. Active high input These pins are used to address the control registers within the chip. Each of the control registers within the chip are assigned a unique address. A control register can be written to or read from by having the page register set to the appropriate page and then setting A[0:4] to the register's address. READ ENABLE. Active low input This pin enables the chip to output the contents of the selected register on the C[0:7] pins when CE is also low. WRITE ENABLE. Active low input This pin enables the chip to write the value on the C[0:7] pins into the selected register when CE is also low. CHIP ENABLE. Active low input This control strobe enables the read or write operation. The contents of the register selected by A[0:5] will be output on C[0:7] when RD is low and CE is low. If WR is low and CE is low, then the selected register will be loaded with the contents of C[0:7]. WRITE MODE. Active high input This pin changes the write timing on the control port so that the data need only be stable relative to the rising edge of either WR or CE. CORE SUPPLY VOLTAGE. These pins are used to supply the core logic. Nominally set at 2.5V. INTERFACE VOLTAGE. These pins are used to set the voltage I/O levels for all pins. Nominally set at 3.3V. Still functional at lower supplies but at reduced speed. GROUND. THERMAL GROUND These pins are used to extract heat from the die and should be connected to the ground plane.
A[0:4]
SCFS A,B,C,D
RD
WR
SUMI[0:21]
CE
SUMO[0:21]
QFLG
VCORE
TMS,TCK,TDI,TDO JTAG INTERFACE. Active high input (TCK, TMS, TDI) and active high tristate output (TDO) pins The JTAG interface, see Section 3.15.
VPAD
GND TGND
(c) 1999-2001 GRAYCHIP,INC.
- 22 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
5.0
CONTROL REGISTERS
The chip is configured and controlled through the use of eight bit control registers. These registers are accessed for reading or writing using the control bus pins (CE, RD, WR, A[0:4], and C[0:7]) described in the previous section. The registers are divided into 16 global registers and 16 paged registers. Addresses 0-15 are reserved for global registers. Addresses 16-31 are used for paged registers. Address 15 is the page register which selects which control registers are accessed by addresses 16 through 31.
5.1
GLOBAL REGISTERS
The 16 global control registers are:
Table 5: GLOBAL CONTROL REGISTERS
ADDRESS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME Sync Mode Interpolation Mode Interpolation Gain Interpolation Byte 0 Interpolation Byte 1 Reset Counter Byte 0 Counter Byte 1 Chan A sync Chan B sync Chan C sync Chan D sync Flush Miscellaneous Status DESCRIPTION Syncs for interpolation, counter, and output. Also ONE_SHOT control. Real in, SplitIQ, gain sync, no symmetry, and diagnostic. Set CIC gain. CIC interpolation count least significant byte. CIC interpolation count most significant bye. Resets for the four channels, resampler, outputs, and global reset. Sync counter least significant byte. Sync counter most significant byte. Syncs for channel A's frequency, phase, NCO, and dither. Syncs for channel B's frequency, phase, NCO, and dither. Syncs for channel C's frequency, phase, NCO, and dither. Syncs for channel D's frequency, phase, NCO, and dither. Flush controls for all four channels. Complex out, msb invert, and various test control bits. Status feedback from chip including: ready/missed flags for channel and resampler, and overflow flags from many places w/in the chip. Page register
15
Page
(c) 1999-2001 GRAYCHIP,INC.
- 23 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
ADDRESS 0:
BIT 0,1 (LSBs) 2,3 4,5 6 7 TYPE R/W R/W R/W R/W R/W
DATA SHEET REV 1.0
Sync Mode, suggested default = 0x69
NAME INT_SYNC COUNTER_SYNC OUTPUT_SYNC USE_ONESHOT ONE_SHOT DESCRIPTION Synchronizes the interpolation control counter. The interpolation counter controls the filtering of each channel. Mode 1 is SIA. Synchronizes the sync counter. This counter is used to generate the periodic "TC" sync pulses. Mode 2 is OS, not TC, for the counter. Mode 1 is SIA. The selected sync is inverted and output on the SO pin. Mode 1 is SIA. The terminal count mode in table 1 is replaced by ONE_SHOT (OS) when this bit is set. The one shot sync signal (OS) is generated when this bit is set. If OS_MODE in register 13 is low, then a one shot pulse (one clock cycle wide) is generated. If OS_MODE is high, then the ONE_SHOT sync is active while this bit is high. This bit must be cleared before another one shot pulse can be generated.
ADDRESS 1:
BIT 0 LSB TYPE R/W
Interpolation Mode, suggested default = 0x00
NAME REAL DESCRIPTION The input samples are real when this bit is set and are up-converted as a single sideband signal. The input samples are treated as complex when this bit is low. The input rate is FCK/4N when this bit is low and is FCK/2N when this bit is high, where FCK is the chip's clock rate and N is the interpolation setting in registers 3 and 4 (See Section 5.4). If double sideband real data is to be up-converted, then the complex mode should be used with the Q-half set to zero. This control bit puts all four channels into the SPLITIQ mode where each channel processes real data at twice the input rate. Two channels work in tandem (A with B and C with D) to process the complex input signal. This mode allows the chip to upconvert two channels at double bandwidth. This mode is used to provide UMTS transmit capability. Selects when the input gain is updated. If 0 the input gain (see page 2) takes effect immediately. If 1, then gain is updated on the first sample following SIB. Special test mode. Set to 0 for normal use. When 0 the PFIR filter is symmetric with 63 taps. When 1, the PFIR filter is non-symmetric with 32 taps. The newest data sample is multiplied by h31. Use the diagnostic ramp as input data. The diagnostic ramp is synchronized by the sync selected by these bits according to table 1. This sync also loads the checksum register. Mode 1 is SIA
1
R/W
SPLIT_IQ
2 3 4 5 6,7
R/W R/W R/W R/W R/W
GAIN_SYNC TEST NOSYM DIAG DIAG_SYNC
ADDRESS 2:
BIT 0-3 4,5 6,7 TYPE R/W R/W R/W
Interpolation Gain, suggested default = 0x09
NAME SCALE BIG_SHIFT UNUSED DESCRIPTION SCALE ranges from 0 to 15. BIG_SHIFT equals 0, 1 or 2.
The CIC filter has a gain which is equal to N4. To remove this gain the CIC outputs are shifted down by (3+SCALE+12*BIG_SHIFT) bits and then rounded to 16 bits before they are sent to the mixer circuit. The value chosen for BIG_SHIFT must also satisfy: 2(12*BIG_SHIFT+18) N4. Overflows due to improper gain settings will go undetected if this relationship is violated. This restriction means that BIG_SHIFT is 0 for N between 8 and 22, BIG_SHIFT is 1 for N between 23 and 181, and BIG_SHIFT is 2 for N between 182 and 1448. The interpolation gain settings apply to all channels in the chip.
(c) 1999-2001 GRAYCHIP,INC.
- 24 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
ADDRESS 3:
BIT 0-7 TYPE R/W
DATA SHEET REV 1.0
Interpolation Byte 0, suggested default = 0x07
NAME INT[0:7] DESCRIPTION The LSBs of the interpolation control word INT. INT is N-1.
ADDRESS 4:
BIT 0-5 6,7 TYPE R/W R/W
Interpolation Byte 1, suggested default = 0x00
NAME INT[8:13] Unused DESCRIPTION The 6 MSBs of the interpolation control word INT. INT is N-1.
Where INT is equal to N-1. The chip interpolates the input data by a factor of 2N for real input data and 4N for complex input data, where N ranges from 8 to 16384. This provides an interpolation range from 32 to 65,536 for complex input signals and 16 to 32,768 for real input signals. NOTE: The chip needs to be flushed each time the interpolation registers are changed. See Section 5.8. Values of N exceeding 1448 should be avoided since they will cause overflow unless the input signal amplitude is correspondingly reduced. For complex output the signal is decimated by two after the CIC and before the mixer. As a result, the effective interpolation amount is only N/2, but the gain needs to be calculated for "N". The interpolation factor applies to all channels in the chip. In the SPLIT_IQ mode (see Section 3.3.4 and bit 1, address 1), INT is set to INT=2N-1, where N ranges from 4 to 8192.
ADDRESS 5:
BIT 0 LSB 1 2 3 4 5 TYPE R/W R/W R/W R/W R/W R/W
Reset Register, Set to 0xff on power up.
NAME RESET_A RESET_B RESET_C RESET_D RESAMPLER_RESET NOCK_RESET DESCRIPTION This bit resets channel A. It is set during power up. While in reset the channel consumes very modest power (uWatts). This bit resets channel B. This bit resets channel C. This bit resets channel D. This bit resets the resampler. Allows output enables to flow through registers in output pads. Set on power up so that all outputs are tristated at power up. The user should reset this bit when ready for outputs to drive. This bit resets the output formatter block. This bit powers down the chip.
6 7
R/W R/W
PAD_RESET GLOBAL_RESET
The reset register powers up to the reset state of 0xff. The register should be set to 0xff during initialization, and then cleared to begin operation. See Section 3.12 for initialization details.
(c) 1999-2001 GRAYCHIP,INC.
- 25 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
ADDRESS 6:
BIT 0-7 TYPE R/W
DATA SHEET REV 1.0
Counter Byte 0, suggested default = 0xff
NAME CNT[0:7] DESCRIPTION The LSBs of the counter cycle period
ADDRESS 7:
BIT 0-7 TYPE R/W
Counter Byte 1, suggested default = 0xff
NAME CNT[8:15] DESCRIPTION The 8 MSBs of the counter cycle period
The chip's internal sync counter counts in cycles of 128(CNT+1) clocks. A terminal count signal (TC) is output at the end of each cycle. The counter can be synchronized to an external sync as specified in the Sync mode Register (See Address 0). If CNT is set so that 128(CNT+1) is a multiple of twice the interpolation ratio (i.e., a multiple of 16N), then the terminal count of this counter can be output on the SO pin and used to periodically synchronize multiple GC4116 chips.
ADDRESS 8: ADDRESS 9: ADDRESS 10: ADDRESS 11:
Channel-A Sync Modes, suggested default = 0x5f Channel-B Sync Modes Channel-C Sync Modes Channel-D Sync Modes
Registers 8,9,10 and 11 control the synchronization modes of the four channels. The sync modes described here are unique to each of the channels. Sync mode 1 is SIB. The sync modes are shown in Table 1 (See Section 3.11).
BIT 0,1 LSB 2,3 4,5 6,7 MSB TYPE R/W R/W R/W R/W NAME FREQ_SYNC PHASE_SYNC NCO_SYNC DITHER_SYNC DESCRIPTION The new frequency setting takes affect on this sync The new phase offset takes affect on this sync The NCO is initialized to the phase setting by this sync The dither circuit is initialized by this sync to zero.
The NCO_SYNC mode is usually set to be always "off", unless the user wants to coherently control the phases of multiple channels. The FREQ_SYNC and PHASE_SYNC modes are typically set to be always "on" so that frequency and phase settings will take effect immediately as they are written into their control registers (See pages 0 and 1). The DITHER_SYNC is used to turn on or off the dithering of the NCO phase. To turn off dithering set the DITHER_SYNC to be always "on" so that it remains initialized to zero. To turn dithering on set the sync to be always "off". During diagnostics the NCO_SYNC and DITHER_SYNC should be set to "TC".
(c) 1999-2001 GRAYCHIP,INC.
- 26 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
ADDRESS 12:
BIT 0,1 LSB 2,3 4,5 6,7 MSB TYPE R/W R/W R/W R/W
DATA SHEET REV 1.0
Channel Flush Register, suggested default = 0x55
NAME FLUSH_A[0:1] FLUSH_B[0:1] FLUSH_C[0:1] FLUSH_D[0:1] DESCRIPTION The flush sync for channel A. The flush sync for channel B. The flush sync for channel C. The flush sync for channel D.
This register controls flushing the four channels. Each channel is flushed when the selected sync occurs. Sync mode 1 is SIA. The sync is selected according to Table 1 in Section 3.11. Each channel needs to be flushed when the chip is being initialized or when the interpolation control is changed. The flush lasts for 8N clocks after the sync occurs. The channel flush syncs will normally be left in a "never" mode. During diagnostics the channels will need to be flushed at the beginning of each sync cycle.
ADDRESS 13:
BIT 0 LSB 1 2 3 TYPE R/W R/W R/W R/W
Miscellaneous Register, Set to zero on power up
NAME DISABLE_AUTO_FLUSH MSB_INVERT COMPLEX_OUT EXT_2XCK DESCRIPTION The chip normally automatically flushes a channel if instability in the channel's CIC filter is detected. If this bit is set the auto flush feature is disabled. Inverts the MSB of the output data (SUMO21) for use with offset binary DACs. Should not be set for chips feeding the sumin port of another GC4116. Complex output is generated with I followed by Q. Interpolation amount is 2N for complex input and N for real input. For test purposes an external 2x clock can be supplied. This control bit enables its use. Normal use will set this bit to zero. For test purposes the internally generated 2x clock can be routed to the soB pin for test. Normal use will set this bit to zero. The absence of a clock for extended times (1mS) can cause a current surge. An internal circuit detects this condition prior to the current surge and puts the chip into a reset state. This control bit disables this feature. Normal use will set this bit to zero. Puts the chip into the GC4117's four separate output mode. Is only valid for the 208 ball GC4117 package. Must be set low for the 160 ball GC4116 package. The ONE_SHOT signal is a level, not a pulse when this bit is set.
4 5
R/W R/W
CK2X_TEST DISABLE_CK_LOSS
6 7
R/W R/w
FOUR_OUT _MODE (GC4117 only) OS_MODE
(c) 1999-2001 GRAYCHIP,INC.
- 27 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
ADDRESS 14:
BIT 0 LSB TYPE R/W
DATA SHEET REV 1.0
Status Register
NAME CHAN_INPUT_READY DESCRIPTION The user sets this bit after loading the input registers. The chip clears this bit when the values have been read and it is time to load new ones. Part of the channel's parallel input handshake protocol. The chip sets this bit If the user has not set the INPUT_READY bit before the chip reads the input registers. This bit high indicates that an error has occurred. Part of the channel's parallel input handshake protocol. The user sets this bit after loading the input registers. The chip clears this bit when the values have been read and it is time to load new ones. Part of the resampler's parallel input handshake protocol. The chip sets this bit If the user has not set the INPUT_READY bit before the chip reads the input registers. This bit high indicates that an error has occurred. Part of the resampler's parallel input handshake protocol. Overflow was detected in the CIC shifter. Overflow was detected in the sumio path at the final rounder. For normal uses this should not occur except in the final chip in a sumpath. In the final chip the D/A loading is often optimized to balance clipping and rounding noise resulting in a SUMIO_OVERFLOW every 10,000 to 100,000 samples. This bit is set by the chip if an overflow is detected in the resampler. This should never happen if the resampler is properly programmed. The chip sets this bit if it detects a clock loss.
1
R/W
CHAN_MISSED
2
R/W
RES_INPUT_READY
3
R/W
RES_MISSED
4 5
R/W R/W
CHAN_OVERFLOW SUMIO_OVERFLOW
6 7
R/W R/W
RES_OVERFLOW CK_LOSS_DETECTED
This register is modified by the chip setting or clearing bits to indicate status of a variety of conditions. The user reads the status register to detect the status and rewrites it to be able to detect the next change in status. The CHAN_INPUT_READY and RES_INPUT_READY bits are used to tell an external processor when to load new input samples. If desired, the CHREQ and RREQ pins can be used as an interrupt to the external processor to tell the processor when to load new samples. The user does not need to set the INPUT_READY bits if interrupts are used. If INPUT_READY is not set, however, the MISSED flag will not be valid. The same input block design is used for channels and the resampler. The resampler always requires complex input data. The channels can accept real input data. The parallel input mode assumes the data are being entered as complex pairs, even when the data are real. To enter real data in the parallel mode, the user must put two real samples into each complex pair, the first sample in the I-half and the second in the Q-half.
ADDRESS 15:
BIT 0-5 6,7 TYPE R/W R/W
Page Register
NAME Page[0:5] Unused DESCRIPTION Page number for addresses 16 through 31.
(c) 1999-2001 GRAYCHIP,INC.
- 28 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
5.2
are:
PAGED REGISTERS
Addresses 16 through 31 are used in pages as determined by the page map register (address 15). The page assignments
Table 6: Page Assignments
PAGE 0 DESCRIPTION Frequency and Phase for Channels A and B Also Checksum And Revision Registers Frequency and Phase for Channels C and D Input Gain Settings Channel Input Registers Resampler Input Registers I/O Control Registers unused Resampler Control Registers Resampler Ratio Registers unused Channel A PFIR Coefficients Channel B PFIR Coefficients Channel C PFIR Coefficients Channel D PFIR Coefficients Resampler Coefficients
1 2 3 4 5 6,7 8 9 10-15 16-19 20-23 24-27 28-31 32-63
(c) 1999-2001 GRAYCHIP,INC.
- 29 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
5.3
FREQUENCY AND PHASE PAGES (PAGES 0 AND 1)
Pages 0 and 1 are used to set the tuning frequencies and phase offsets of the four channels. Page 0 also contains the read
only checksum diagnostic register and the mask revision register. The 32 bit frequency control word is defined as: FREQ = 232F/FCK where F is the desired tuning frequency
and FCK is the chip's clock rate (not the CK2X rate). Use positive frequency values to upconvert signals. Use negative frequency values to upconvert inverted spectrums. The 32 bit 2's complement frequency words are entered as four bytes, the least significant byte in the lowest address, the most significant in the highest address. The 16 bit phase offset is defined as: PHASE = 216P/2 where P is the desired phase in radians from 0 to 2.
PAGE 0: Channels A and B ADDRESSES 16, 17, 18, and 19: Frequency Channel A
ADDRESS 16 17 18 19 TYPE R/W R/W R/W R/W NAME FREQ_A[0:7] FREQ_A[8:15] FREQ_A[16:23] FREQ_A[24:31] DESCRIPTION Byte 0 (LSBs) of FREQ_A Byte 1 of FREQ_A Byte 2 of FREQ_A Byte 3 (MSBs) of FREQ_A
ADDRESSES 20, 21: Phase Channel A
ADDRESS 20 21 TYPE R/W R/W NAME PHASE_A[0:7] PHASE_A[8:15] DESCRIPTION Byte 0 (LSBs) of PHASE_A Byte 1 (MSBs) of PHASE_A
ADDRESSES 24, 25, 26, and 27: Frequency Channel B
ADDRESS 24 25 26 27 TYPE R/W R/W R/W R/W NAME FREQ_B[0:7] FREQ_B[8:15] FREQ_B[16:23] FREQ_B[24:31] DESCRIPTION Byte 0 (LSBs) of FREQ_B Byte 1 of FREQ_B Byte 2 of FREQ_B Byte 3 (MSBs) of FREQ_B
ADDRESSES 28, 29: Phase Channel B
ADDRESS 20 21 TYPE R/W R/W NAME PHASE_B[0:7] PHASE_B[8:15] DESCRIPTION Byte 0 (LSBs) of PHASE_B Byte 1 (MSBs) of PHASE_B
ADDRESSES 30, 31: Checksum and Revision Registers
ADDRESS 30 31 TYPE Ronly Ronly NAME CHECKSUM REVISION DESCRIPTION The 8 bit diagnostic checksum. See Section 3.14. The 8 bit Revision number. See Section 3.16.
(c) 1999-2001 GRAYCHIP,INC.
- 30 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
PAGE 1: Channels C and D ADDRESSES 16, 17, 18, and 19: Frequency Channel C
ADDRESS 16 17 18 19 TYPE R/W R/W R/W R/W NAME FREQ_C[0:7] FREQ_C[8:15] FREQ_C[16:23] FREQ_C[24:31] DESCRIPTION Byte 0 (LSBs) of FREQ_C Byte 1 of FREQ_C Byte 2 of FREQ_C Byte 3 (MSBs) of FREQ_C
DATA SHEET REV 1.0
ADDRESSES 20, 21: Phase Channel C
ADDRESS 20 21 TYPE R/W R/W NAME PHASE_C[0:7] PHASE_C[8:15] DESCRIPTION Byte 0 (LSBs) of PHASE_C Byte 1 (MSBs) of PHASE_C
ADDRESSES 24, 25, 26, and 27: Frequency Channel D
ADDRESS 24 25 26 27 TYPE R/W R/W R/W R/W NAME FREQ_D[0:7] FREQ_D[8:15] FREQ_D[16:23] FREQ_D[24:31] DESCRIPTION Byte 0 (LSBs) of FREQ_D Byte 1 of FREQ_D Byte 2 of FREQ_D Byte 3 (MSBs) of FREQ_D
ADDRESSES 28, 29: Phase Channel D
ADDRESS 20 21 TYPE R/W R/W NAME PHASE_D[0:7] PHASE_D[8:15] DESCRIPTION Byte 0 (LSBs) of PHASE_D Byte 1 (MSBs) of PHASE_D
5.4
INPUT GAIN PAGE (PAGE 2)
This page contains independent gain settings for the four channels. Gain is G/128, where G is in two's complement format. Page two registers are listed in the table below.
ADDRESSES 16, 17, 18, and 19: Input Gain
ADDRESS 16 17 18 19 TYPE R/W R/W R/W R/W NAME GAIN_A[0:7] GAIN_B[0:7] GAIN_C[0:7] GAIN_D[0:7] DESCRIPTION The gain (G) for channel A The gain (G) for channel B The gain (G) for channel C The gain (G) for channel D
(c) 1999-2001 GRAYCHIP,INC.
- 31 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
5.5
CHANNEL INPUT PAGE (PAGE 3)
Page 3 is used to enter input data in the parallel mode (see PARALLEL_A,B,C and D in address of the IO control page).
ADDRESSES 16 to 31: Channel Inputs
ADDRESS 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W NAME CHAN_A_I[0:7] CHAN_A_I[8:15] CHAN_A_QI[0:7] CHAN_A_Q[8:15] CHAN_B_I[0:7] CHAN_B_I[8:15] CHAN_B_QI[0:7] CHAN_B_Q[8:15] CHAN_C_I[0:7] CHAN_C_I[8:15] CHAN_C_QI[0:7] CHAN_C_Q[8:15] CHAN_D_I[0:7] CHAN_D_I[8:15] CHAN_D_QI[0:7] CHAN_D_Q[8:15] DESCRIPTION The 8 LSBs of Channel A's I input The 8 MSBs of Channel A's I input The 8 LSBs of Channel A's Q input The 8 MSBs of Channel A's Q input The 8 LSBs of Channel A's I input The 8 MSBs of Channel A's I input The 8 LSBs of Channel A's Q input The 8 MSBs of Channel A's Q input The 8 LSBs of Channel A's I input The 8 MSBs of Channel A's I input The 8 LSBs of Channel A's Q input The 8 MSBs of Channel A's Q input The 8 LSBs of Channel D's I input The 8 MSBs of Channel D's I input The 8 LSBs of Channel D's Q input The 8 MSBs of Channel D's Q input
The CHAN_INPUT_READY and CHAN_MISSED control bits in the status register (address 14) can be used as "handshake" signals between the chip and the external processor providing the data. The external processor sets CHAN_INPUT_READY after it has loaded the channel inputs into page 3. The chip will then clear CHAN_INPUT_READY when it has used the new inputs. The external processor can monitor CHAN_INPUT_READY to determine when it is time to load new inputs. If the external processor has not set CHAN_INPUT_READY when the chip wants to use the inputs, then it will set CHAN_MISSED to let the external processor know that a handshake error has occurred and input samples have been missed. The external processor can also use the CHREQ output as an interrupt to know new samples are needed.
(c) 1999-2001 GRAYCHIP,INC.
- 32 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
5.6
RESAMPLER INPUT PAGE (PAGE 4)
Page 4 is used to enter input data in the parallel mode (see PARALLEL_A,B,C and D in address of the IO control page).
ADDRESSES 16 to 31: Resampler Inputs
ADDRESS 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W NAME RES_A_I[0:7] RES_A_I[8:15] RES_A_QI[0:7] RES_A_Q[8:15] RES_B_I[0:7] RES_B_I[8:15] RES_B_QI[0:7] RES_B_Q[8:15] RES_C_I[0:7] RES_C_I[8:15] RES_C_QI[0:7] RES_C_Q[8:15] RES_D_I[0:7] RES_D_I[8:15] RES_D_QI[0:7] RES_D_Q[8:15] DESCRIPTION The 8 LSBs of Resampler Channel A's I input The 8 MSBs of Resampler Channel A's I input The 8 LSBs of Resampler Channel A's Q input The 8 MSBs of Resampler Channel A's Q input The 8 LSBs of Resampler Channel A's I input The 8 MSBs of Resampler Channel A's I input The 8 LSBs of Resampler Channel A's Q input The 8 MSBs of Resampler Channel A's Q input The 8 LSBs of Resampler Channel A's I input The 8 MSBs of Resampler Channel A's I input The 8 LSBs of Resampler Channel A's Q input The 8 MSBs of Resampler Channel A's Q input The 8 LSBs of Resampler Channel D's I input The 8 MSBs of Resampler Channel D's I input The 8 LSBs of Resampler Channel D's Q input The 8 MSBs of Resampler Channel D's Q input
The RES_INPUT_READY and RES_MISSED control bits in the status register (address 14) can be used as "handshake" signals between the chip and the external processor providing the data. The external processor sets RES_INPUT_READY after it has loaded the channel inputs into page 3. The chip will then clear RES_INPUT_READY when it has used the new inputs. The external processor can monitor RES_INPUT_READY to determine when it is time to load new inputs. If the external processor has not set RES_INPUT_READY when the chip wants to use the inputs, then it will set RES_MISSED to let the external processor know that a handshake error has occurred and input samples have been missed. The external processor can also use the RREQ output as an interrupt to know new samples are needed.
(c) 1999-2001 GRAYCHIP,INC.
- 33 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
5.7
I/O CONTROL PAGE (PAGE 5)
Page 5 controls the formatting and IO speed of channel and resampler inputs, resampler output, sumout and enables for the various outputs. Page five registers are listed in the table below:
Table 7: IO Control Page Registers (Page 5)
ADDRESS 16 17 18 19 20 21 NAME Channel Input Mode Resampler Input Mode Resampler Output Mode Sum IOMode Serial Controller Modes Serial Controller Frame Count Serial Controller Frame Delays A and B Serial Controller Frame Delays C and D Output Enables DESCRIPTION Channel input format (packed, clock and frame polarity, parallel or serial). Resampler input format (packed, clock and frame polarity, parallel or serial). Controls resampler output clock rate, sync, polarity, and frame polarity. Sum IO path rounding, delay, shifting, and clear. Controls request clock rate, sync, and polarity. Sets the serial controller's frame length.
22
Delay positions for serial controller frame strobes A and B.
23
Delay positions for serial controller frame strobes C and D.
24
Output enables for sum, resampler, request, frame strobes, sync out, and request polarities. Sets the clock rate for the resampler computations
25 26-31
Resampler Clock Divider Unused
ADDRESS 16:
BIT 0 LSB TYPE R/W
Channel Input Mode Register, suggested default = 0x01
NAME PACKED DESCRIPTION Puts the channel serial inputs into the 32 bit transfer mode where each complex pair is packed into 32 bit words. The complex pair is formatted as I word in the upper 16 bits and the Q word in the lower 16 bits. Each word is formatted as MSB first.
1 2 3 4
R/W R/W R/W R/W
Unused SCK_POL SFS_POL PARALLEL_A The SIN Input bits and SFS frame strobes are clocked in on the trailing edge of SCK when this bit is set. The rising edge is used when this bit is low. The SFS signal is treated as active low when this bit is set. Otherwise the signal is treated as active high. The parallel/Serial control for channel input A. When low input for channel A is taken from the serial port. When high it is taken from the channel input page registers. The parallel/Serial control for channel B. The parallel/Serial control for channel C. The parallel/Serial control for channel D.
5 6 7
R/W R/W R/W
PARALLEL_B PARALLEL_C PARALLEL_D
(c) 1999-2001 GRAYCHIP,INC.
- 34 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
I/O CONTROL PAGE 5 (continue) ADDRESS 17:
BIT 0 LSB TYPE R/W
DATA SHEET REV 1.0
Resampler Input Mode Register, suggested default = 0x03
NAME RES_PACKED DESCRIPTION Puts the resampler serial inputs into the 32 bit transfer mode where each complex pair is packed into 32 bit words. The complex pair is formatted as I word in the upper 16 bits and the Q word in the lower 16 bits. Each word is formatted as MSB first. Set to zero when the serial controller is being used with the resampler and is set to 1 when it is used with the channels. The RIN Input bits and RFS frame strobes are clocked in on the trailing edge of RSCK when this bit is set. The rising edge is used when this bit is low. The RFS signal is treated as active low when this bit is set. Otherwise the signal is treated as active high. The parallel/Serial control for resampler input A. When low input for resampler channel A is taken from the serial port. When high it is taken from the resampler input page registers. The parallel/Serial control for resampler channel B. The parallel/Serial control for resampler channel C. The parallel/Serial control for resampler channel D.
1 2 3 4
R/W R/W R/W R/W
SC_MODE RCK_POL RFS_POL RES_PARALLEL_A
5 6 7
R/W R/W R/W
RES_PARALLEL_B RES_PARALLEL_C RES_PARALLEL_D
ADDRESS 18:
BIT 0-3 LSB 4 5 6,7 TYPE R/W R/W R/W R/W
Resampler Output Mode Register, suggested default = 0x51
NAME ROCK_RATE ROCK_POL ROFS_POL ROCK_SYNC DESCRIPTION The resampler serial output clock rate is ROCK = CK/(1+ROCK_RATE). The serial clock changes on the rising edge of CK when ROCK_RATE is even. Resampler serial output clock polarity. Inverts ROCK. When ROCK_POL=0 and ROCK_RATE=0, ROCK is a slightly delayed version of CK. Resampler frame strobe polarity. If low, the frame strobe pulses high for one RCK period prior to the first transmitted bit. If high the frame strobe pulses low. Sync control for the resampler output clock. The sync settings are 0 =never; 1 = SIA; 2 =SIB; 3=Always.
ADDRESS 19:
BIT 0-2 LSB TYPE R/W
Sum IOMode Register, suggested default = 0x80
NAME SUM_ROUND DESCRIPTION Round the output to 22-(2*SUM_ROUND) bits. The remaining low order bits are cleared. In normal use SUM_ROUND is 0 for all chips in a sum path except the final one. The final one is programmed to match the number of bits used by the D/A or other follow-on devices. Shift the sum output up by SUM_SCALE bits prior to rounding. In normal use SUM_SCALE is 0 for all chips in a sum path except the final one. The final one is typically programmed so that the output has a 14 dB crest factor. The latency sumin to sumout is 8 cycles. Enabling this bit adds 8 cycles of latency to the output of the 4 internal channels to match the delay from one previous chip. Clears sumin data so that regardless of the input to the sumin port it does not affect the sum output.
3-5
R/W
SUM_SCALE
6
R/W
SUM_DELAY
7
R/W
SUM_CLEAR
(c) 1999-2001 GRAYCHIP,INC.
- 35 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
I/O CONTROL PAGE 5 (continue) ADDRESS 20:
BIT 0-3 LSB TYPE R/W
DATA SHEET REV 1.0
Serial Controller Output Mode Register, suggested default = 0x51
NAME SCCK_RATE DESCRIPTION The SCCK output rate is set to SCCK = CK / SCCK_RATE. The serial clock is always approximately 50% duty cycle. The serial clock changes on the rising edge of CK when SCCK_RATE even. Serial controller clock polarity. Inverts REQSCK. When SCCK_POL=0 and SCCK_RATE=0, RCK is a slightly delayed version of CK. Serial controller frame strobe polarity. If low, the frame strobe pulses high for one SCCK period prior to the first transmitted bit. If high the frame strobe pulses low. Sync control for the SCCK clock. The sync settings are 0 = never; 1=SIA; 2=SIB; 3=Always.
4 5
R/W R/W
SCCK_POL SCFS_POL
6,7
R/W
SCCK_SYNC
ADDRESS 21:
BIT 0-7 TYPE R/W
Serial Controller Frame Count, suggested default = 0x17
NAME SC_FRAME_CNT DESCRIPTION The initial value for the serial controller frame counter. Sets the serial controller's frame length.
The frame counter is preloaded with this value and held there until SCSTART. Once SCSTART is received the counter is decremented with each SCCK clock. When the lower four bits are zero and the upper four bits match one of the SC_FRAME_DELAY values, then the respective frame strobe is output. If unpacked then bit 4 of the counter is forced to zero for the match, resulting in a pair of strobes separated by 16 clocks for each frame strobe delay value.
ADDRESS 22:
BIT 0-3 4-7 TYPE R/W R/W
SC Frame Delays A and B, suggested default = 0x11
NAME SC_FRAME_DELAY_A SC_FRAME_DELAY_B DESCRIPTION Delay value for serial controller output frame strobe A. Delay value for serial controller output frame strobe B.
ADDRESS 23:
BIT 0-3 4-7 TYPE R/W R/W
SC Frame Delays C and D, suggested default = 0x11
NAME SC_FRAME_DELAY_C SC_FRAME_DELAY_D DESCRIPTION Delay value for serial controller output frame strobe C. Delay value for serial controller output frame strobe D.
(c) 1999-2001 GRAYCHIP,INC.
- 36 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
I/O CONTROL PAGE 5 (continue) ADDRESS 24:
BIT 0 LSB 1 2 3 4 5 6 7 TYPE R/W R/W R/W R/W R/W R/W R/W R/W
DATA SHEET REV 1.0
Output Enable Register, suggested default = 0x3f
NAME SUM_EN RES_EN REQ_EN SC_EN SO_EN Unused CHREQ_POL RREQ_POL Invert the channel request. This is useful when the request signal is used as a frame strobe with some DSPs (such as Lucent 1620). Invert the resampler request. This is useful when the request signal is used as a frame strobe with some DSPs (such as Lucent 1620). DESCRIPTION Enable sumout pins. Enable resampler serial data out, resampler frame strobes, and resampler serial clocks. Enable resampler and channel request outputs. Enable serial controller serial clocks and frame strobes. Enable the sync output (SO) pin
ADDRESS 25:
BIT 0-7 TYPE R/W
Resampler Clock Divide Register, Must be set to 0x00
NAME RES_CLK_DIV DESCRIPTION Resampler clock division.
The resampler clock divider is not functional and must be set to zero.
(c) 1999-2001 GRAYCHIP,INC.
- 37 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
5.8
RESAMPLER CONTROL PAGE (PAGE 8)
This page controls the resampler. The address assignments are:
Table 8: Resampler Control Registers
ADDRESS 16 17 18 19 20 21 22 23 24-31 NAME N-channels N-Multiplies Filter Select Final Shift Serial Map Ratio Sync unused Ratio Map Unused Maps ratios to resampler channels DESCRIPTION Sets the number of resampler channels and filters Sets the number of multiplies per output Maps filters to resampler channels Sets the final gain shift Maps serial inputs to resampler channels Synchronizes the ratio selection changes.
ADDRESS 16:
BIT 0-1 LSB TYPE R/W
N-Channels Out Register, Suggested default = 0x23
NAME NC DESCRIPTION Must be set to NC=NCHAN-1, where NCHAN is the number of resampler channels to be generated. A value of NC=0 means one resampler channel. A value of NC=1 means two resampler channels. Use a value of NC=3 for either three or four resampler channels. A value of 2 is illegal and will produce erroneous results. Must be set to NF=NFILTER-1, where NFILTER is the number of resampler filters. Used to partition the resampler coefficient RAM. A value of NF=0 means one filter (normal case). A value of NF=1 means two filters. A value of NF=3 means four filters. A value of 2 is illegal. The resampler is synchronized to this sync source. This sync clears the delay accumulators in all channels at the same time. The sync modes are: 0,1 and 5 are "never", 2=SIA, 3=SIB, 4=OS, and 6,7 are "always".
2-3
R/W
NF
4-6
R/W
RES_SYNC
7 MSB
R/W
Unused
ADDRESS 17:
BIT 0-5 LSB TYPE R/W
N-Multiplies Register, Suggested default = 0x0E
NAME NM DESCRIPTION Must be set to NM=NMULT-1, where NMULT is the number of resampler multiplies. The minimum legal value is NM=5, the maximum is NM=63 but typically the maximum will be set by other constraints (see Section 3.7.4). In the case of a single channel output the minimum value is NM=6. The resampler filter is presumed to be symmetric unless this bit is set.
6 7 MSB
R/W R/W
NO_SYM_RES Unused
(c) 1999-2001 GRAYCHIP,INC.
- 38 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
RESAMPLER CONTROL PAGE 8 (continue) ADDRESS 18:
BIT 0-1 LSB 2-3 4-5 6-7 MSB TYPE R/W R/W R/W R/W
DATA SHEET REV 1.0
Filter Select Register, Suggested default = 0x00
NAME FILTER_SEL_0 FILTER_SEL_1 FILTER_SEL_2 FILTER_SEL_3 DESCRIPTION The filter map for resampler channel 0. This select which of the NFILTER filters to use for this channel. Must be less than or equal to NFILTER The filter map for resampler channel 1. The filter map for resampler channel 2. The filter map for resampler channel 3.
ADDRESS 19:
BIT 0-3 LSB 4-5 6,7 (MSB TYPE R/W R/W R/W
Final Shift Register, Suggested default = 0x14
NAME FINAL_SHIFT ROUND Unused DESCRIPTION The final shift up applied to all resampler channels before rounding and outputting. Legal values are 0-15. Round the output to 12 (ROUND=0), 16 (ROUND=1), 20 bits (ROUND=2) or 24 bits (ROUND=3). Note, ROUND must be set to 1 (16 bits).
ADDRESS 20:
BIT 0-1 LSB 2-3 4-5 6-7 MSB TYPE R/W R/W R/W R/W
Serial Map Register, Suggested default = 0xE4
NAME SERIAL_MAP_A SERIAL_MAP_B SERIAL_MAP_C SERIAL_MAP_D DESCRIPTION The map for serial input A. This tells the hardware which resampler channel serial input A should be directed to. The map for serial input B. The map for serial input C. The map for serial input D.
This register maps resampler serial inputs to resampler channels. For most applications this will be a simple map of input A to resampler channel 0, input B to resampler channel 1, etc. However, for two channel and one channel modes the mapping is non-standard. The resampler input buffer requires that serial input D is always active, so in the single channel mode serial input D must be mapped to resampler channel 0. This requires the serial map register to be set to 0x00. For two channels, serial inputs C and D will be active and they should be mapped to resampler channels 0 and 1. This requires the serial map register to be set to 0x40.
ADDRESS 21:
BIT 0-3 LSB 4-6 TYPE R/W R/W
Ratio Sync, Suggested default = 0x20
NAME TEST RATIO_SYNC DESCRIPTION For Factory test purposes, must be set to zero. Changes to the ratio map (address 23) are synchronized to this sync source. The sync modes are: 0,1 and 5 are "never", 2=SIA, 3=SIB, 4=OS, and 6,7 are "always".
7 MSB
R/W
Unused
When processing complex input signals partial results are computed in adjacent channels that must be summed together to produce a meaningful result. This control bit informs the resampler to save the data presented to it's input and add it to the next sample presented (if the chip is properly set up this will be from the next channel). In this manner the real and imaginary portions of the input are rejoined prior to resampling.
(c) 1999-2001 GRAYCHIP,INC.
- 39 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
RESAMPLER CONTROL PAGE 8 (continue) ADDRESS 23:
BIT 0-1 LSB 2-3 4-5 6-7 MSB TYPE R/W R/W R/W R/W
DATA SHEET REV 1.0
Ratio Map Register Suggested default = 0x00
NAME RATIO_MAP_0 RATIO_MAP_1 RATIO_MAP_2 RATIO_MAP_3 DESCRIPTION The ratio map for resampler channel 0. This tells the hardware which resampler ratio should be use for resampler channel 0. The ratio map for resampler channel 1. The ratio map for resampler channel 2. The ratio map for resampler channel 3.
The default ratio maps select ratio 0 for all four channels. The resampler in the GC4116 must use the same ratio for all resampler channels, which means that the valid values for the ratio map are 0x00, 0x55, 0xAA and 0xFF to select ratio 0, 1, 2 or 3. The ratio maps can also be used to synchronously switch between resampling ratios. This allows the chip's resampler to be used in timing loops where the ratio must toggle between several values which have been programmed into the chip.
5.9
RESAMPLER RATIO PAGE (PAGE 9)
This page stores four resampler ratios to be used by the resampler channels. Each ratio is the 32 bit ratio of the input sample rate to the output sample rate with an implicit decimal point six bits down from the top. The total range for the ratio is then 0 to 63. The hardware limits the decimation to be less than 32 (hence the MSB of the 32 bit word should always be zero). RATIO = 226(Input Sample Rate)/(Output Sample Rate)
Table 9: Resampler Ratio Page
ADDRESS 16 17 18 19 20 21 22 23 NAME RATIO_0 (LSBs) RATIO_0 RATIO_0 RATIO_0 (MSBs) RATIO_1 (LSBs) RATIO_1 RATIO_1 RATIO_1 (MSBs) ADDRESS 24 25 26 27 28 29 30 31 NAME RATIO_2 (LSBs) RATIO_2 RATIO_2 RATIO_2 (MSBs) RATIO_3 (LSBs) RATIO_3 RATIO_3 RATIO_3 (MSBs)
The ratio map register selects which ratio is used by the resampler.
(c) 1999-2001 GRAYCHIP,INC.
- 40 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
5.10
PFIR COEFFICIENT PAGES (PAGES 16 to 31)
The user programmable filter PFIR coefficients are stored using pages16 to 19 for channel A, pages 20 to 23 for channel B, pages 24 to 27 for channel C, and pages 28 to 31 for channel D.
Table 10: PFIR Coefficient Pages
Pages 16, 20, 24 or 28 Address Description
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 h0 LSBs (end tap) h0 MSBs (end tap) h1 LSBs h1 MSBs h2 LSBs h2 MSBs h3 LSBs h3 MSBs h4 LSBs h4 MSBs h5 LSBs h5 MSBs h6 LSBs h6 MSBs h7 LSBs h7 MSBs
Pages 17, 21, 25 or 29 Description
h8 LSBs h8 MSBs h9 LSBs h9 MSBs h10 LSBs h10 MSBs h11 LSBs h11 MSBs h12 LSBs h12 MSBs h13 LSBs h13 MSBs h14 LSBs h14 MSBs h15 LSBs h15 MSBs
Pages 18, 22, 26 or 30 Description
h16 LSBs h16 MSBs h17 LSBs h17 MSBs h18 LSBs h18 MSBs h19 LSBs h19 MSBs h20 LSBs h20 MSBs h21 LSBs h21 MSBs h22 LSBs h22 MSBs h23 LSBs h23 MSBs
Pages 19, 23, 27 or 31 Description
h24 LSBs h24 MSBs h25 LSBs h25 MSBs h26 LSBs h26 MSBs h27 LSBs h27 MSBs h28 LSBs h28 MSBs h29 LSBs h29 MSBs h30 LSBs h30 MSBs h31 LSBs (center tap) h31 MSBs (center tap)
Coefficient h0 is the first coefficient and coefficient h31 is the center coefficient of the filter's impulse response. The 16 bit 2's complement coefficients are stored in two bytes, least significant byte first, for example, the LSBs of coefficient 0 are stored in address 16 and the MSBs in address 17. TO LOAD A COEFFICIENT THE USER MUST WRITE THE LSBYTE FIRST FOLLOWED BY THE MSBYTE. Unknown values will be written into the LSBs if the MSB is written first. The coefficient registers are read/write.
(c) 1999-2001 GRAYCHIP,INC.
- 41 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
5.11
RESAMPLER COEFFICIENT PAGES (PAGES 32-63)
These pages store the 256 resampler coefficients. Storing resampler coefficient values is similar to storing the coefficients for the PFIR filters. The resampler coefficients are 12 bits with the 8 LSBs written in one address, and the upper 4 bits written as the 4 LSBs of the next address. When reading back resampler coefficients the top four bits of the second address always read back zero. The resampler coefficient RAM must be written in blocks of eight addresses (four coefficients). Writes to the RAM occur when a write is done to addresses 23 or 31. Supplying coefficients in sequential order will write correctly to the RAM. If just a portion of the resampler coefficient RAM is to be updated, then one must write in blocks of the eight addresses 16 to 23, or 24 to 31. Writing to less than eight addresses will either result in no change to the RAM or unknown changes to some coefficients. TO LOAD A COEFFICIENT THE USER MUST WRITE IN BLOCKS OF FOUR COEFFICIENTS. ONE MUST WRITE TO ADDRESSES 16-22 THEN ADDRESS 23 OR TO ADDRESSES 24-30 THEN ADDRESS 31.
Table 11: Resampler Coefficient Pages (Single filter mode)
Page Address 32
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 h0 h0 h1 h1 h2 h2 h3 h3 h4 h4 h5 h5 h6 h6 h7 h7
33
h8 h8 h9 h9 h10 h10 h11 h11 h12 h12 h13 h13 h14 h14 h15 h15
34
h16 h16 h17 h17 h18 h18 h19 h19 h20 h20 h21 h21 h22 h22 h23 h23
35
h24 h24 h25 h25 h26 h26 h27 h27 h28 h28 h29 h29 h30 h30 h31 h31
36
h32 h32 h33 h33 h34 h34 h35 h35 h36 h36 h37 h37 h38 h38 h39 h39
37
h40 h40 h41 h41 h42 h42 h43 h43 h44 h44 h45 h45 h46 h46 h47 h47
38
h48 h48 h49 h49 h50 h50 h51 h51 h52 h52 h53 h53 h54 h54 h55 h55
39
h56 h56 h57 h57 h58 h58 h59 h59 h60 h60 h61 h61 h62 h62 h63 h63
40
h64 h64 h65 h65 h66 h66 h67 h67 h68 h68 h69 h69 h70 h70 h71 h71
41
h72 h72 h73 h73 h74 h74 h75 h75 h76 h76 h77 h77 h78 h78 h79 h79
42
h80 h80 h81 h81 h82 h82 h83 h83 h84 h84 h85 h85 h86 h86 h87 h87
43
h88 h88 h89 h89 h90 h90 h91 h91 h92 h92 h93 h93 h94 h94 h95 h95
44
h96 h96 h97 h97 h98 h98 h99 h99 h100 h100 h101 h101 h102 h102 h103 h103
45
h104 h104 h105 h105 h106 h106 h107 h107 h108 h108 h109 h109 h110 h110 h111 h111
46
h112 h112 h113 h113 h114 h114 h115 h115 h116 h116 h117 h117 h118 h118 h119 h119
47
h120 h120 h121 h121 h122 h122 h123 h123 h124 h124 h125 h125 h126 h126 h127 h127
Page Address 48
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 h128 h128 h129 h129 h130 h130 h131 h131 h132 h132 h133 h133 h134 h134 h135 h135
49
h136 h136 h137 h137 h138 h138 h139 h139 h140 h140 h141 h141 h142 h142 h143 h143
50
h144 h144 h145 h145 h146 h146 h147 h147 h148 h148 h149 h149 h150 h150 h151 h151
51
h152 h152 h153 h153 h154 h154 h155 h155 h156 h156 h157 h157 h158 h158 h159 h159
52
h160 h160 h161 h161 h162 h162 h163 h163 h164 h164 h165 h165 h166 h166 h167 h167
53
h168 h168 h169 h169 h170 h170 h171 h171 h172 h172 h173 h173 h174 h174 h175 h175
54
h176 h176 h177 h177 h178 h178 h179 h179 h180 h180 h181 h181 h182 h182 h183 h183
55
h184 h184 h185 h185 h186 h186 h187 h187 h188 h188 h189 h189 h190 h190 h191 h191
56
h192 h192 h193 h193 h194 h194 h195 h195 h196 h196 h197 h197 h198 h198 h199 h199
57
h200 h200 h201 h201 h202 h202 h203 h203 h204 h204 h205 h205 h206 h206 h207 h207
58
h208 h208 h209 h209 h210 h210 h211 h211 h212 h212 h213 h213 h214 h214 h215 h215
59
h216 h216 h217 h217 h218 h218 h219 h219 h220 h220 h221 h221 h222 h222 h223 h223
60
h224 h224 h225 h225 h226 h226 h227 h227 h228 h228 h229 h229 h230 h230 h231 h231
61
h232 h232 h233 h233 h234 h234 h235 h235 h236 h236 h237 h237 h238 h238 h239 h239
62
h240 h240 h241 h241 h242 h242 h243 h243 h244 h244 h245 h245 h246 h246 h247 h247
63
h248 h248 h249 h249 h250 h250 h251 h251 h252 h252 h253 h253 h254 h254 h255 h255
Table 11 shows the coefficient register assignments when there is a single filter (NF=0). For two filters (NF=1), the two filters are interleaved, i.e., the heven in Table 11 will contain one filter and hodd will contain the other. Four four filters (NF=3), the four filters are interleaved, i.e., h0, h4, h8, ... is the first filter, h1, h5, ... is the second, etc.
(c) 1999-2001 GRAYCHIP,INC.
- 42 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
6.0 6.1
SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS
Table 12: Absolute Maximum Ratings
CAUTION: Exceeding the absolute maximum ratings (min or max) may cause permanent damage to the part. These are stress only ratings and are not intended for operation. PARAMETER Pad Ring Supply Voltage Core Supply Voltage Input voltage (undershoot and overshoot) Storage Temperature Junction Temperature under operation Lead Soldering Temperature (10 seconds) ESD Classification SYMBOL VPAD VCORE VIN TSTG TJ MIN -0.3 -0.3 -0.5 -65 MAX 4.1 3.0 VPAD+0.5 150 125 300 UNITS V V V NOTES
C C C
1
Class 3A Human Body Model (4 kV) (JESD22-A114-B) Class 4 Charged Device Model (1 kV) (JESD22-C101-A) Class 2
Moisture Sensitivity
1. The circuit is designed for junction temperatures up to 125C. Sustained operation above 125C junction temperature will reduce long term reliability.
6.2
RECOMMENDED OPERATING CONDITIONS
Table 13: Recommended Operating Conditions
PARAMETER Pad Ring Supply Voltage Core Supply Voltage Temperature Ambient, no air flow Junction Temperature SYMBOL VPAD VCORE TA TJ MIN 3.0 2.3 -40 MAX 3.6 2.7 +85 100 UNITS V V NOTES 1 1 1 2
C C
1. DC and AC specifications in Tables 15 and 16 are production tested over these ranges. 2. Thermal management may be required for full rate operation, See Table 22 below and Section 7.4.
6.3
THERMAL CHARACTERISTICS
Table 14: Thermal Data
160 PBGA THERMAL CONDUCTIVITY SYMBOL 0.5 Watt Theta Junction to Ambient Theta Junction to Case Note: Air flow will reduce ja and is highly recommended. 1 Watt TBD TBD UNITS
JA JC
TBD TBD
C/W C/W
(c) 1999-2001 GRAYCHIP,INC.
- 43 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
6.4
POWER CONSUMPTION
The power consumption is a function of the operating mode of the chip. The following equation estimates the typical power supply current for the chip. Chip to chip variation is typically +/- 5%. The AC specification in Table 16 is the current tested for during production test and represents the absolute maximum power supply current.
FCK IPAD (TYP) = ( VPAD ) ------- ( Nout ) ( Cout ) 4 VCORE F CK 450 ICORE (TYP) = ------------ ------------- 20 + A 30 + -------- + 15R mA 2.5 100M N
Where A is the number of active channels (0 to 4), N is the CIC decimation ratio, FCKis the clock rate, Nout is the number of active output data pins, and Cout is the average capacitive load on each data pin. R is one if the resampler is active, and is 0 if the resampler is off (RES_RESET=1 in address 5). The equation assumes random data transition density of 1 rising edge per four clock cycles.
6.5
DC CHARACTERISTICS
Table 15: DC Operating Conditions (-40 to 85C case unless noted)
VPAD = 3.0 to 3.6V PARAMETER SYMBOL MIN Voltage input low Voltage input high Voltage output low (IOL = 2mA) Voltage output high (IOH = -2mA) Leakage current (VIN = 0V or VPAD) Inputs or Outputs in tristate condition Pullup current (VIN = 0V) (TDI, TMS, TCK) Quiescent supply current, ICORE or IPAD (VIN=0 or VIN=VPAD, Address 0 = F0, LVDS=0) Data input capacitance (All inputs except CK) Clock input capacitance (CK input)
Notes: Currents are measured at nominal voltages, high temperature (85C). Voltages are measured at low speed. Output voltages are measured with the indicated current load Test Levels: I. Controlled by design and process and not directly tested or recommended practice. II. Verified on initial part evaluation. III. 100% tested at room temperature, sample tested at hot and cold. IV. 100% tested at hot, sample tested cold. V. 100% tested at hot and cold.
UNITS MAX 0.8 2.3 0.5 2.4 1 V V V V uA
TEST LEVEL IV IV IV IV IV
VIL VIH VOL VOH | IIN | | IPU | ICCQ CIN CCK 4 (typical) 5
35 2
uA mA
IV IV
pF pF
I I
13 (typical)
(c) 1999-2001 GRAYCHIP,INC.
- 44 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
6.6
AC CHARACTERISTICS
Table 16: AC Characteristics (-40 TO +85oC Case, unless noted)
2.3 V to 2.7 V TEST LEVEL IV IV II I IV IV IV IV IV IV 5 ns IV
PARAMETER
SYMBOL MIN MAX 100
UNITS
Clock Frequency Clock low or high period Clock Duty Cycle (tCKH as a percentage of the clock period) Clock rise and fall times (VIL to VIH) Input setup before CK goes high (IN or SI) Input hold time after CK goes high Serial Clock Frequency Serial Clock low or high period Serial Data Setup before SCK Serial Data Hold from SCK Data output delay from rising edge of CK. (OUT, CHREQ, RSREQ, QFLG or SO) Output skew between SCCK and SCFS Output skew between ROCK and ROFS or ROUT JTAG Clock Frequency JTAG Clock low or high period JTAG Input (TDI or TMS) setup before TCK goes high JTAG Input (TDI or TMS) hold time after TCK goes high JTAG output (TDO) delay from rising edge of TCK. Control Setup before both CE, WR or RD go low (See section 3.1) Control data setup during writes (edge mode). (See section 3.1) Control hold after CE, WR or RD go high. (See section 3.1) Control strobe (CE or WR) pulse width (Write operation). (See section 3.1) Control recovery time between reads or writes. (See section 3.1) Control output delay CE and RD low to C (Read Operation). (See section 3.1) Control tristate delay after CE and RD go high. (See section 3.1) Supply current (FCK =100MHz, N=9, all channels active). (See section 6.4)
Notes:
FCK tCKL/H
Note 1 3
MHz ns
70 tRF tSU tHD FSCK tSCKL/H tSSU tSHD tDLY tSCSK tROSK FJCK tJCKL/H tJSU tHD tDLY tCSU tEWCSU tCHD tCSPW tREC tCDLY tCZ ICORE 2 4 1 20 20 12 4 395 2 0.8 0 3 2 0.8 1 100 2
% ns ns ns MHz ns ns
-2 -2 0 10 5 10
2.5 2.5 40
ns ns MHz ns ns ns
IV IV IV IV IV IV IV IV IV IV IV IV IV I IV
10
ns ns ns ns ns ns ns ns mA
1. The minimum clock rate must satisfy FCK/(4N) > 10KHz, where N is the CIC interpolation ratio. 2. Timing between signals is measured from mid-voltage (VPAD/2) to mid-voltage. Output loading is a 50 Ohm transmission line. Test Levels: I. Controlled by design and process and not directly tested or recommended practice. II. Verified on initial part evaluation. III. 100% tested at room temperature, sample tested at hot and cold. IV. 100% tested at hot, sample tested cold. V. 100% tested at hot and cold.
(c) 1999-2001 GRAYCHIP,INC.
- 45 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
6.7 6.8
APPLICATION NOTES POWER AND GROUND CONNECTIONS
The GC4116 chip is a very high performance chip which requires solid power and ground connections to avoid noise on the VCC, VPAD and GND pins. If possible the GC4116 chip should be mounted on a circuit board with dedicated power and ground planes and with at least two decoupling capacitors (0.01 f), one for VCC and one for VPAD adjacent to each side of the GC4116 chip. If dedicated power and ground planes are not possible, then the user should place decoupling capacitors across as many VCC or VPAD and GND pairs as is practical.
IMPORTANT
The GC4116 chip may not operate properly if these power and ground guidelines are violated.
6.9
STATIC SENSITIVE DEVICE
The GC4116 chips are fabricated in a high performance CMOS process which is sensitive to the high voltage transients caused by static electricity. These parts can be permanently damaged by static electricity and should only be handled in static free environments. The parts are tested to exceed 2 Kv human body model.
6.10
MOISTURE SENSITIVE PACKAGE
The GC4016 come in level 2 moisture sensitive packages. Dry pack storage is required prior to assembly.
6.11
THERMAL MANAGEMENT
The parameters in Section 6.0 are tested at a junction temperature of 100C. In any case, the junction temperature must be kept below 125 C for reliable operation. To determine the junction temperature, the user should calculate the chip's power dissipation using the equation for supply current in Section 6.4 and then use the package's thermal conductivity shown in Section 6.3. The junction temperature is calculated by adding the operating ambient temperature (or case temperature) to the product of the power consumption times the thermal conductivity. For example, the GC4116 chip operating in the GSM mode described in Section 7.8, consumes 0.XX Watts of power. The junction to ambient rise of the 160 BGA package is XXX degrees per Watt. This represents a rise of 25 degrees over ambient. This means that under these conditions the ambient temperature has to be less than 75C to keep the junction temperature below 100C. Air flow will decrease the thermal resistance by 10% to 40%, allowing ambient temperatures between 78C and 85C. Increasing the decimation ratio (N) or decreasing the number of active channels (A) will also allow a higher ambient temperature.
(c) 1999-2001 GRAYCHIP,INC.
- 46 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
6.12
REFERENCE DESIGNS
Figure 16 illustrates how to use the GC4116 without the Resampler. The Serial Controller generates the serial clock and frame strobes used to clock the data out of the user's data source ASIC or DSP chip. This configuration guarantees that the data will be received by the GC4116 at the correct times. If a serial TDM bus is used as the data source, then the single serial data source is connected to all four serial inputs of the GC4116 chip, and the CHREQ output from the GC4116 chip is used as the frame start signal to the data source chip. The four serial frame strobes are used by the GC4116 chip to identify the appropriate time slots within the TDM stream.
DATA FROM OTHER GC4116 CHIPS SERIAL CLOCK INPUT USER ASIC OR DSP CHIP DATA SOURCE SERIAL FRAME STROBE INPUTS SERIAL DATA SOURCES
22 SUMI[0:21] SUMO[0:21]
22
M10 N10 L14 L11 M8 M9 N14 L12 H14 G13 E14 F12 M5
SCKD SCKC SCKB SCKA SFSD SFSC SFSB SFSA SIND SINC SINB SINA SCSTART
GC4116 QUAD DUC CHIP
CHANNEL I/O
CHREQ
P6
MODULATED DATA TO DAC OR OTHER GC4116 CHIPS
SCCK1 SCCK0 SERIAL CONTROLLER I/O SCFSD SCFSC SCFSB SCFSA RREQ ROCK1 ROCK0
P11 M12 P7 N9 N12 M11 M6 P10 N11
N6 M14 M13 J13 K12 N7 P9 K13 L13 J11 G12 G11 E13 5 CONTROL 8
RSTART RCKD RCKC RCKB RCKA RFSD RFSC RFSB RFSA RIND RINC RINB RINA A[0:4] C[0:7] RESAMPLER I/O
ROFS1 ROFS0 ROUTD ROUTC ROUTB ROUTA
P12 M7 H13 H11 F14 E12
INTERFACE VPAD FROM SO ON OTHER GC4116 CHIPS CLOCK
M1 P2 L2 N3 J3 J1 J14 J12
RD WR CE WRMODE SIB SIA CK CK2X
CONTROL I/O
SO
J2
TO SIA OR SIB INPUTS ON OTHER GC4116 CHIPS
GND
Figure 16. Reference Design Without the Resampler
(c) 1999-2001 GRAYCHIP,INC.
- 47 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
Figure 17 illustrates how the resampler section is used with the GC4116. As in the previous configuration, TDM serial data can be handled by connecting all four resampler serial inputs to the single TDM source and using the RREQ output as the start of frame signal. In this configuration the resampler outputs drive the channel inputs directly, and the Serial Controller is used to drive the resampler input timing.
DATA FROM OTHER GC4116 CHIPS
22 SUMI[0:21] SUMO[0:21]
22
M10 N10 L14 L11 M8 M9 N14 L12 H14 G13 E14 F12 M5
SCKD SCKC SCKB SCKA SFSD SFSC SFSB SFSA SIND SINC SINB SINA SCSTART
GC4116 QUAD DUC CHIP
CHANNEL I/O
CHREQ
P6
MODULATED DATA TO DAC OR OTHER GC4116 CHIPS
SCCK1 SCCK0 SERIAL CONTROLLER I/O SCFSD SCFSC SCFSB SCFSA RREQ ROCK1 ROCK0
P11 M12 P7 N9 N12 M11 M6 P10 N11
N6 M14 M13 J13 K12 N7 P9 K13 L13 J11 G12 G11 E13 5 CONTROL 8
RSTART RCKD RCKC RCKB RCKA RFSD RFSC RFSB RFSA RIND RINC RINB RINA A[0:4] C[0:7] RESAMPLER I/O
SERIAL CLOCK INPUT USER ASIC OR DSP CHIP DATA SOURCE SERIAL FRAME STROBE INPUTS SERIAL DATA SOURCES
ROFS1 ROFS0 ROUTD ROUTC ROUTB ROUTA
P12 M7 H13 H11 F14 E12
INTERFACE VPAD FROM SO ON OTHER GC4116 CHIPS CLOCK
M1 P2 L2 N3 J3 J1 J14 J12
RD WR CE WRMODE SIB SIA CK CK2X
CONTROL I/O
SO
J2
TO SIA OR SIB INPUTS ON OTHER GC4116 CHIPS
GND
Figure 17. Reference Design Using the Resampler
(c) 1999-2001 GRAYCHIP,INC. - 48 APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
The following Sections are in progress. Contact GRAYCHIP for the latest information
DATA SHEET REV 1.0
6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22
EXAMPLE PFIR FILTER SETS EXAMPLE RESAMPLER CONFIGURATIONS NOISE ANALYSIS EXAMPLE GSM APPLICATION EXAMPLE IS-136 DAMPS APPLICATION EXAMPLE IS-95 NB-CDMA APPLICATION EXAMPLE UMTS WB-CDMA APPLICATION DIAGNOSTICS OUTPUT TEST CONFIGURATION INPUT TEST CONFIGURATION
(c) 1999-2001 GRAYCHIP,INC.
- 49 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
Graychip reserves the right to make changes in circuit design and/or specifications at any time without notice. The user is cautioned to verify that datasheets are current before placing orders. Information provided by Graychip is believed to be accurate and reliable. No responsibility is assumed by Graychip for its use, nor for any infringement of patents or other rights of third parties which may arise from its use. No license is granted by implication or otherwise under any patent rights of Graychip.
(c) 1999-2001 GRAYCHIP,INC.
- 50 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
GC4116 REGISTER ASSIGNMENT QUICK REFERENCE GUIDE.
Page
Global
Address
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Name
Sync Mode Int Mode Int Gain Int Byte 0 Int Byte 1 Reset Counter Byte 0 Counter Byte 1 Chan A Sync Chan B Sync Chan C Sync Chan D Sync Flush Miscellaneous Status Page
7(MSB)
ONE_SHOT
6
USE_OS
5
4
3
2
1
0(LSB)
Suggested Default
E9 then 69 00 09 07
OUTPUT_SYNC (SIA)
COUNTER_SYNC (SIA) TEST GAIN_SYNC SCALE INT[0:7]
INT_SYNC (SIA) SPLIT_IQ REAL
DIAG_SYNC (SIA) -
DIAG
NOSYM
BIG_SHIFT
GLOBAL PAD_RESET NOCK_RESET RES_RESET
INT[8:13] RESET_D
00
RESET_B
RESET_C
RESET_A
FF then 00 00 00
CNT[0:7] CNT[7:15] DITHER_SYNC (SIB) DITHER_SYNC (SIB) DITHER_SYNC (SIB) DITHER_SYNC (SIB) FLUSH_D (SIA) OS_MODE CK_LOSS 32 bit channel A tuning frequency, LSBs in 16, MSBs in 19, FREQ = 232F/FCK 16 bit channel A phase, LSBs in 20, MSBs in 21, PHASE=216P/2 32 bit channel B tuning frequency, LSBs in 24, MSBs in 27, FREQ = 232F/FCK 16 bit channel B phase, LSBs in 28, MSBs in 29, PHASE=216P/2 CHECKSUM REVISION 32 bit channel C tuning frequency, LSBs in 16, MSBs in 19, FREQ = 232F/FCK 16 bit channel C phase, LSBs in 20, MSBs in 21, PHASE=216P/2 32 bit channel D tuning frequency, LSBs in 24, MSBs in 27, FREQ = 232F/FCK 16 bit channel D phase, LSBs in 28, MSBs in 29, PHASE=216P/2 8 bit input gain (G) for channel A. GAIN = G/128 8 bit input gain (G) for channel B. GAIN = G/128 8 bit input gain (G) for channel C. GAIN = G/128S 8 bit input gain (G) for channel D. GAIN = G/128 Channel A Input Data, I-Half. LSBs in 16, MSBs in 17 Channel A Input Data, Q-Half. LSBs in 18, MSBs in 19 Channel B Input Data, I-Half. LSBs in 20, MSBs in 21 Channel B Input Data, Q-Half. LSBs in 22, MSBs in 23 Channel C Input Data, I-Half. LSBs in 24, MSBs in 25 Channel C Input Data, Q-Half. LSBs in 26, MSBs in 27 Channel D Input Data, I-Half. LSBs in 28, MSBs in 29 Channel D Input Data, Q-Half. LSBs in 30, MSBs in 31 Resampler A Input Data, I-Half. LSBs in 16, MSBs in 17 Resampler A Input Data, Q-Half. LSBs in 18, MSBs in 19 Resampler B Input Data, I-Half. LSBs in 20, MSBs in 21 Resampler B Input Data, Q-Half. LSBs in 22, MSBs in 23 Resampler C Input Data, I-Half. LSBs in 24, MSBs in 25 Resampler C Input Data, Q-Half. LSBs in 26, MSBs in 27 Resampler D Input Data, I-Half. LSBs in 28, MSBs in 29 Resampler D Input Data, Q-Half. LSBs in 30, MSBs in 31 32 PFIR Coefficients for channel A. Load LSBs in even addresses, MSBs in odd addresses 32 PFIR Coefficients for channel B. Load LSBs in even addresses, MSBs in odd addresses 32 PFIR Coefficients for channel C. Load LSBs in even addresses, MSBs in odd addresses 32 PFIR Coefficients for channel D. Load LSBs in even addresses, MSBs in odd addresses 4_OUT_MODE RES_OVFLW NCO_SYNC (SIB) NCO_SYNC (SIB) NCO_SYNC (SIB) NCO_SYNC (SIB) FLUSH_C (SIA) DIS_CK_LOSS SUMIO_OVFL CK2X_TEST CHAN_OVFLW PHASE_SYNC (SIB) PHASE_SYNC (SIB) PHASE_SYNC (SIB) PHASE_SYNC (SIB) FLUSH_B (SIA) EXT_CK2X RES_MISSED CMPLX_OUT RES_IN_RDY FREQ_SYNC (SIB) FREQ_SYNC (SIB) FREQ_SYNC (SIB) FREQ_SYNC (SIB) FLUSH_A (SIA) MSB_INVERT CHAN_MISSD NO_AUTO_FL CHAN_IN_RDY
5F 5F 5F 5F 55 80 00 00 00000000 0000 00000000 0000 read only read only 00000000 0000 00000000 0000 80 80 80 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PAGE
Page 0
16,17,18,19 FREQ_A
20,21 PHASE_A Frequency 24,25,26,27 FREQ_B and Phase 28,29 PHASE_B A,B 30 Checksum 31 Revision
Page 1 16,17,18,19 FREQ_C Frequency 20,21 PHASE_C and 24,25,26,27 FREQ_D Phase A,B 28,29 PHASE_D Page 2 Input Gain 16 17 18 19 Page 3 Channel Inputs 16,17 18,19 20,21 22,23 24,25 26,27 28,29 30,31 Page 4 Resampler Inputs 16,17 18,19 20,21 22,23 24,25 26,27 28,29 30,31 P 16-19 F 20-23 I R 24-27 28-31 16-31 16-31 16-31 16-31 GAIN_A GAIN_B GAIN_C GAIN_D CHAN_A_I CHAN_A_Q CHAN_B_I CHAN_B_Q CHAN_C_I CHAN_C_Q CHAN_D_I CHAN_D_Q RES_A_I RES_A_Q RES_B_I RES_B_Q RES_C_I RES_C_Q RES_D_I RES_D_Q PFIR_A Taps PFIR_B Taps PFIR_C Taps PFIR_D Taps
SYNC MODE 0 1 2
SYNC SOURCE off (never asserted) SIA or SIB, See each sync for (SIA) or (SIB) TC (OS if USE_OS is set) on (always active)
REV 1.0
3
APRIL 27, 2001
GC4116 REGISTER ASSIGNMENT QUICK REFERENCE GUIDE
Page
I O C O N T R O L 7
Address
16 17 18 19 20 21 22 23 24 25
Name
Channel Input Resampler Input Resampler Out Sum IO Mode Serial Controller SC Frame Count SC FS Delay A,B SC FS Delay C,D Output Enables Res Clock Divder N-Channels N-Multiplies Filter Select Final Shift Channel Map Ratio Sync unused Ratio Map Res Ratio 0 Res Ratio 1 Res Ratio 2 Res Ratio 3 Filter Taps
7(MSB)
PARALLEL_D RES_PAR_D
6
PARALLEL_C RES_PAR_C
5
PARALLEL_B RES_PAR_B ROFS_POL
4
PARALLEL_A RES_PAR_A ROCK_POL SUM_SCALE
3
SFS_POL RFS_POL
2
SCK_POL RCK_POL
1
SC_MODE
0(LSB)
PACKED RES_PACKED
Suggested Default
01 03 51 80 51 17
ROCK_SYNC (See below) SUM_CLEAR SUM_DELAY
ROCK_RATE SUM_ROUND SCCK_RATE
SCCK_SYNC (See Below)
SCFS_POL
SCCK_POL SC_FRAME_CNT
SC_FRAME_DELAY_B SC_FRAME_DELAY_D RREQ_POL CHREQ_POL SO_EN SC_EN
SC_FRAME_DELAY_A SC_FRAME_DELAY_C REQ_EN RES_EN SUM_EN
11 11 1F 00
RES_CLK_DIV clock rate = 2*FCK/(1+RES_CLK_DIV) NO_SYM_RES FILTER_SEL_3 CHAN_MAP_D FILTER_SEL_2 ROUND (12B,16B, 20B,24B) CHAN_MAP_C RATIO_SYNC RATIO_MAP_3 RATIO_MAP_2 RATIO_MAP_1 RATIO_MAP_0 CHAN_MAP_B TEST (must be 0) RES_SYNC NF=(NFILTER-1) NM=(NMULT-1) FILTER_SEL_1 FINAL_SHIFT CHAN_MAP_A FILTER_SEL_0 NC =(NCHAN-1)
R E S A M P L E R
8
16 17 18 19 20 21 22 23
23 0E 00 34 E4 70 00 00 04000000 04000000 04000000 04000000
9
16-19 20-23 24-27 28-31
RATIO_0, Resampler ratio 0. RATIO = 226(Resampler input sample rate)/(Resampler output sample rate) RATIO_1, Resampler ratio 1. RATIO_2, Resampler ratio 2. RATIO_3, Resampler ratio 3. Resampler Coefficients, 8 LSBs in even addresses, 4 MSBs in odd addresses. (Must be loaded in the blocks 16-23 and 24-31)
32-63
16-31
GAIN
=
G PFIR_SUM -------- --------------------------- 128 65536
{ N4 2 -( SCALE + 12 x BIG_SHIFT + 3 ) } { 2SUM_SCALE - 7 }
Description Interpolation control counter. Sets timing of CHREQ. Default Sync Circuit 1(SIA) GAIN_SYNC
RES_GAIN =
RES_SUM ( ---------------------------------------------- ) ( 2 FINAL_SHIFT ) 32768 x NDELAY
Sync Circuit INT_SYNC
Mode 1 SIA
Mode 1 SIB
Description A single bit sync selection. GAIN_SYNC=0 means the gain is applied immediately. GAIN_SYNC=1 means the gain is applied after SIB. Selects when to start the diagnostic ramp and to store the diagnostic checksum. Selects when new frequency settings take effect. Selects when new phase settings take effect. Reset the NCO phase accumulator
Default 0
COUNTER_ SYNC
SIA
Internal sync counter. Generates TC sync. Mode 2 is always ONE_SHOT The output sync (SO) selection. Syncs the resampler's serial output clock. Mode 2 is SIB. Syncs the serial controller's serial output clock. Mode 2 is SIB. Syncs the resampler during initialization Selects when a new resampler ratio takes effect.
2 (OS) DIAG_SYNC
SIA
2 (TC)
OUTPUT_ SYNC ROCK_SYNC
SIA
2 (TC) FREQ_SYNC
SIB
3 (on)
SIA
PHASE_SYNC
SIB
3 (on)
SCCK_SYNC
SIA
NCO_SYNC
SIB
0 (off)
RES_SYNC
Note 1
DITHER_ SYNC FLUSH _ (A,B,C,D)
SIB
Clears the NCO dither circuit.
0 (off)
RATIO_SYNC
Note 1
SIA
Starts a flush of the channel
1 (SIA)
Note 1: These use a 3 bit sync mode selection where modes 0,1 and 5 are "off", mode 2 is SIA, mode 3 is SIB, mode 4 is ONE_SHOT, and modes 6 and 7 are "on".
REV 1.0
APRIL 27, 2001

▲Up To Search▲

Price & Availability of GC4116

	To Download GC4116 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .